System for the Remote Execution of Applications

ABSTRACT

A data processing system is presented that is configured as a server in a client-server configuration for executing applications that a client in the client-server configuration can offload as execution tasks for execution on the server. The data processing system includes a reconfigurable processor, a storage device that stores configuration files for the applications, and a host processor that is coupled to the storage device and to the reconfigurable processor. The host processor is configured to receive an execution task of the execution tasks with an identifier of an application from the client, retrieve a configuration file that is associated with the application from the storage device using the identifier of the application, configure the reconfigurable processor with the configuration file, and start execution of the application on the reconfigurable processor, whereby the reconfigurable processor provides output data of the execution of the application to the client.

RELATED APPLICATIONS AND DOCUMENTS

This application claims the benefit of U.S. Provisional Patent Application No. 63/330,742, entitled, “A System for the Remote Execution of Applications” filed on 13 Apr. 2022. The provisional application is hereby incorporated by reference for all purposes.

This application also is related to the following papers and commonly owned applications:

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No. 11,256,987 B1, filed Jun. 2, 2021, entitled         “MEMORY EFFICIENT DROPOUT, WITH REORDERING OF DROPOUT MASK         ELEMENTS;”     -   U.S. Nonprovisional patent application Ser. No. 16/890,841,         filed Jun. 2, 2020, entitled “ANTI-CONGESTION FLOW CONTROL FOR         RECONFIGURABLE PROCESSORS;”     -   U.S. Nonprovisional patent application Ser. No. 17/023,015, now         U.S. Pat. No. 11,237,971 B1, filed Sep. 16, 2020, entitled         “COMPILE TIME LOGIC FOR DETECTING STREAMING COMPATIBLE AND         BROADCAST COMPATIBLE DATA ACCESS PATTERNS;”     -   U.S. Nonprovisional patent application Ser. No. 17/031,679,         filed Sep. 24, 2020, entitled “SYSTEMS AND METHODS FOR MEMORY         LAYOUT DETERMINATION AND CONFLICT RESOLUTION;”     -   U.S. Nonprovisional patent application Ser. No. 17/175,289, now         U.S. Pat. No. 11,126,574 B1, filed Feb. 12, 2021, entitled         “INSTRUMENTATION PROFILING FOR RECONFIGURABLE PROCESSORS;”     -   U.S. Nonprovisional patent application Ser. No. 17/371,049,         filed Jul. 8, 2021, entitled “SYSTEMS AND METHODS FOR EDITING         TOPOLOGY OF A RECONFIGURABLE DATA PROCESSOR;”     -   U.S. Nonprovisional patent application Ser. No. 16/922,975,         filed Jul. 7, 2020, entitled “RUNTIME VIRTUALIZATION OF         RECONFIGURABLE DATA FLOW RESOURCES;”     -   U.S. Nonprovisional patent application Ser. No. 16/996,666,         filed Aug. 18, 2020, entitled “RUNTIME PATCHING OF CONFIGURATION         FILES;”     -   U.S. Nonprovisional patent application Ser. No. 17/214,768, now         U.S. Pat. No. 11,200,096 B1, filed Mar. 26, 2021, entitled         “RESOURCE ALLOCATION FOR RECONFIGURABLE PROCESSORS;”     -   U.S. Nonprovisional patent application Ser. No. 17/127,818, now         U.S. Pat. No. 11,182,264 B1, filed Dec. 18, 2020, entitled         “INTRA-NODE BUFFER-BASED STREAMING FOR RECONFIGURABLE         PROCESSOR-AS-A-SERVICE (RPAAS);”     -   U.S. Nonprovisional patent application Ser. No. 17/127,929, now         U.S. Pat. No. 11,182,221 B1, filed Dec. 18, 2020, entitled         “INTER-NODE BUFFER-BASED STREAMING FOR RECONFIGURABLE         PROCESSOR-AS-A-SERVICE (RPAAS);”     -   U.S. Nonprovisional patent application Ser. No. 17/185,264,         filed Feb. 25, 2021, entitled “TIME-MULTIPLEXED USE OF         RECONFIGURABLE HARDWARE;”     -   U.S. Nonprovisional patent application Ser. No. 17/216,647, now         U.S. Pat. No. 11,204,889 B1, filed Mar. 29, 2021, entitled         “TENSOR PARTITIONING AND PARTITION ACCESS ORDER;”     -   U.S. Nonprovisional patent application Ser. No. 17/216,650, now         U.S. Pat. No. 11,366,783 B1, filed Mar. 29, 2021, entitled         “MULTI-HEADED MULTI-BUFFER FOR BUFFERING DATA FOR PROCESSING;”     -   U.S. Nonprovisional patent application Ser. No. 17/216,657, now         U.S. Pat. No. 11,263,170 B1, filed Mar. 29, 2021, entitled         “LOSSLESS TILING IN CONVOLUTION NETWORKS—PADDING BEFORE TILING,         LOCATION-BASED TILING, AND ZEROING-OUT;”     -   U.S. Nonprovisional patent application Ser. No. 17/384,515,         filed Jul. 23, 2021, entitled “LOSSLESS TILING IN CONVOLUTION         NETWORKS—MATERIALIZATION OF TENSORS;”     -   U.S. Nonprovisional patent application Ser. No. 17/216,651, now         U.S. Pat. No. 11,195,080 B1, filed Mar. 29, 2021, entitled         “LOSSLESS TILING IN CONVOLUTION NETWORKS—TILING CONFIGURATION;”     -   U.S. Nonprovisional patent application Ser. No. 17/216,652, now         U.S. Pat. No. 11,227,207 B1, filed Mar. 29, 2021, entitled         “LOSSLESS TILING IN CONVOLUTION NETWORKS—SECTION BOUNDARIES;”     -   U.S. Nonprovisional patent application Ser. No. 17/216,654, now         U.S. Pat. No. 11,250,061 B1, filed Mar. 29, 2021, entitled         “LOSSLESS TILING IN CONVOLUTION NETWORKS—READ-MODIFY-WRITE IN         BACKWARD PASS;”     -   U.S. Nonprovisional patent application Ser. No. 17/216,655, now         U.S. Pat. No. 11,232,360 B1, filed Mar. 29, 2021, entitled         “LOSSLESS TILING IN CONVOLUTION NETWORKS—WEIGHT GRADIENT         CALCULATION;”     -   U.S. Nonprovisional patent application Ser. No. 17/364,110,         filed Jun. 30, 2021, entitled “LOSSLESS TILING IN CONVOLUTION         NETWORKS—TILING CONFIGURATION FOR A SEQUENCE OF SECTIONS OF A         GRAPH;”     -   U.S. Nonprovisional patent application Ser. No. 17/364,129,         filed Jun. 30, 2021, entitled “LOSSLESS TILING IN CONVOLUTION         NETWORKS—TILING CONFIGURATION BETWEEN TWO SECTIONS;”     -   “U.S. Nonprovisional patent application Ser. No. 17/364,141,         filed Jun. 30, 2021, entitled ““LOSSLESS TILING IN CONVOLUTION         NETWORKS—PADDING AND RE-TILLING AT SECTION BOUNDARIES;”     -   U.S. Nonprovisional patent application Ser. No. 17/384,507,         filed Jul. 23, 2021, entitled “LOSSLESS TILING IN CONVOLUTION         NETWORKS—BACKWARD PASS;”     -   U.S. Provisional Patent Application No. 63/107,413, filed Oct.         29, 2020, entitled “SCANNABLE LATCH ARRAY FOR STRUCTURAL TEST         AND SILICON DEBUG VIA SCANDUMP;”     -   U.S. Provisional Patent Application No. 63/165,073, filed Mar.         23, 2021, entitled “FLOATING POINT MULTIPLY-ADD, ACCUMULATE UNIT         WITH CARRY-SAVE ACCUMULATOR IN BF16 AND FLP32 FORMAT;”     -   U.S. Provisional Patent Application No. 63/166,221, filed Mar.         25, 2021, entitled “LEADING ZERO AND LEADING ONE DETECTOR         PREDICTOR SUITABLE FOR CARRY-SAVE FORMAT;”     -   U.S. Provisional Patent Application No. 63/190,749, filed May         19, 2021, entitled “FLOATING POINT MULTIPLY-ADD, ACCUMULATE UNIT         WITH CARRY-SAVE ACCUMULATOR;”     -   U.S. Provisional Patent Application No. 63/174,460, filed Apr.         13, 2021, entitled “EXCEPTION PROCESSING IN CARRY-SAVE         ACCUMULATION UNIT FOR MACHINE LEARNING;”     -   U.S. Nonprovisional patent application Ser. No. 17/397,241, now         U.S. Pat. No. 11,429,349 B1, filed Aug. 9, 2021, entitled         “FLOATING POINT MULTIPLY-ADD, ACCUMULATE UNIT WITH CARRY-SAVE         ACCUMULATOR;”     -   U.S. Nonprovisional patent application Ser. No. 17/216,509, now         U.S. Pat. No. 11,191,182 B1, filed Mar. 29, 2021, entitled         “UNIVERSAL RAIL KIT;”     -   U.S. Nonprovisional patent application Ser. No. 17/379,921, now         U.S. Pat. No. 11,392,740 B2, filed Jul. 19, 2021, entitled         “DATAFLOW FUNCTION OFFLOAD TO RECONFIGURABLE PROCESSORS;”     -   U.S. Nonprovisional patent application Ser. No. 17/379,924, now         U.S. Pat. No. 11,237,880 B1, filed Jul. 19, 2021, entitled         “DATAFLOW ALL-REDUCE FOR RECONFIGURABLE PROCESSOR SYSTEMS;”     -   U.S. Nonprovisional patent application Ser. No. 17/378,342, now         U.S. Pat. No. 11,556,494 B1, filed Jul. 16, 2021, entitled         “DEFECT REPAIR FOR A RECONFIGURABLE DATA PROCESSOR;”     -   U.S. Nonprovisional patent application Ser. No. 17/378,391, now         U.S. Pat. No. 11,327,771 B1, filed Jul. 16, 2021, entitled         “DEFECT REPAIR CIRCUITS FOR A RECONFIGURABLE DATA PROCESSOR;”     -   U.S. Nonprovisional patent application Ser. No. 17/378,399, now         U.S. Pat. No. 11,409,540 B1, filed Jul. 16, 2021, entitled         “ROUTING CIRCUITS FOR DEFECT REPAIR FOR A RECONFIGURABLE DATA         PROCESSOR;”     -   U.S. Provisional Patent Application No. 63/220,266, filed Jul.         9, 2021, entitled “LOGIC BIST AND FUNCTIONAL TEST FOR A CGRA;”     -   U.S. Provisional Patent Application No. 63/195,664, filed Jun.         1, 2021, entitled “VARIATION-TOLERANT VARIABLE-LENGTH         CLOCK-STRETCHER MODULE WITH IN-SITU END-OF-CHAIN DETECTION         MECHANISM;”     -   U.S. Nonprovisional patent application Ser. No. 17/338,620, now         U.S. Pat. No. 11,323,124 B1, filed Jun. 3, 2021, entitled         “VARIABLE-LENGTH CLOCK STRETCHER WITH CORRECTION FOR GLITCHES         DUE TO FINITE DLL BANDWIDTH;”     -   U.S. Nonprovisional patent application Ser. No. 17/338,625, now         U.S. Pat. No. 11,239,846 B1, filed Jun. 3, 2021, entitled         “VARIABLE-LENGTH CLOCK STRETCHER WITH CORRECTION FOR GLITCHES         DUE TO PHASE DETECTOR OFFSET;”     -   U.S. Nonprovisional patent application Ser. No. 17/338,626, now         U.S. Pat. No. 11,290,113 B1, filed Jun. 3, 2021, entitled         “VARIABLE-LENGTH CLOCK STRETCHER WITH CORRECTION FOR DIGITAL DLL         GLITCHES;”     -   U.S. Nonprovisional patent application Ser. No. 17/338,629, now         U.S. Pat. No. 11,290,114 B1, filed Jun. 3, 2021, entitled         “VARIABLE-LENGTH CLOCK STRETCHER WITH PASSIVE MODE JITTER         REDUCTION;”     -   U.S. Nonprovisional patent application Ser. No. 17/405,913, now         U.S. Pat. No. 11,334,109 B1, filed Aug. 18, 2021, entitled         “VARIABLE-LENGTH CLOCK STRETCHER WITH COMBINER TIMING LOGIC;”     -   U.S. Provisional Patent Application No. 63/230,782, filed Aug.         8, 2021, entitled “LOW-LATENCY MASTER-SLAVE CLOCKED STORAGE         ELEMENT;”     -   U.S. Provisional Patent Application No. 63/236,218, filed Aug.         23, 2021, entitled “SWITCH FOR A RECONFIGURABLE DATAFLOW         PROCESSOR;”     -   U.S. Provisional Patent Application No. 63/236,214, filed Aug.         23, 2021, entitled “SPARSE MATRIX MULTIPLIER;”     -   U.S. Provisional Patent Application No. 63/389,767, filed Jul.         15, 2022. entitled “PEER-TO-PEER COMMUNICATION BETWEEN         RECONFIGURABLE DATAFLOW UNITS;”     -   U.S. Provisional Patent Application No. 63/405,240, filed Sep.         9, 2022, entitled “PEER-TO-PEER ROUTE THROUGH IN A         RECONFIGURABLE COMPUTING SYSTEM.”         All of the related application(s) and documents listed above are         hereby incorporated by reference herein for all purposes.

FIELD OF THE TECHNOLOGY DISCLOSED

The present technology relates to a system, and more particularly, to a data processing system with a reconfigurable processor, a host processor, and a storage device. The data processing system is configured as a server in a client-server configuration for executing a plurality of applications that a client in the client-server configuration can offload as execution tasks for execution on the server.

BACKGROUND

The subject matter discussed in this section should not be assumed to be prior art merely as a result of its mention in this section. Similarly, a problem mentioned in this section or associated with the subject matter provided as background should not be assumed to have been previously recognized in the prior art. The subject matter in this section merely represents different approaches, which in and of themselves can also correspond to implementations of the claimed technology.

Reconfigurable processors, including FPGAs, can be configured to implement a variety of functions more efficiently or faster than might be achieved using a general-purpose processor executing a computer program. So-called coarse-grained reconfigurable architectures (CGRAs) are being developed in which the configurable units in the array are more complex than used in typical, more fine-grained FPGAs, and may enable faster or more efficient execution of various classes of functions. For example, CGRAs have been proposed that can enable implementation of low-latency and energy-efficient accelerators for machine learning and artificial intelligence workloads.

Such reconfigurable processors, and especially CGRAs, often include specialized hardware elements such as computing resources and device memory that operate in conjunction with one or more software elements such as a CPU and attached host memory in deep learning applications.

Deep learning is a subset of machine learning algorithms that are inspired by the structure and function of the human brain. Most deep learning algorithms involve artificial neural network architectures, in which multiple layers of neurons each receive input from neurons in a prior layer or layers, and in turn influence the neurons in the subsequent layer or layers.

Training a neural network involves determining weights that are associated with the neural network, and making inference involves using a trained neural network to compute results by processing input data based on weights associated with the trained neural network.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to like parts throughout the different views. Also, the drawings are not necessarily to scale, with an emphasis instead generally being placed upon illustrating the principles of the technology disclosed. In the following description, various implementations of the technology disclosed are described with reference to the following drawings.

FIG. 1 is a diagram of an illustrative data processing system including a coarse-grained reconfigurable (CGR) processor, CGR processor memory, and a host processor.

FIG. 2 is a diagram of an illustrative computer, including an input device, a processor, a storage device, and an output device.

FIG. 3 is a diagram of an illustrative reconfigurable processor including a top-level network (TLN) and two CGR arrays.

FIG. 4 is a diagram of an illustrative CGR array including CGR units and an array-level network (ALN).

FIG. 5 illustrates an example of a pattern memory unit (PMU) and a pattern compute unit (PCU), which may be combined in a fused-control memory unit (FCMU).

FIG. 6 is a diagram of an illustrative compute environment in which applications are provided a unified interface to a pool of reconfigurable data flow resources such that the pool of reconfigurable data flow resources is available to the applications as a single reconfigurable processor.

FIG. 7A is a diagram of an illustrative client-server configuration for executing a plurality of applications that a client in the client-server configuration can offload as execution tasks for execution on the server.

FIG. 7B is a diagram of illustrative communications in a client-server configuration in which a client offloads execution tasks for execution on the server.

FIG. 8 is a diagram of an illustrative client-server configuration in which an illustrative server has input buffers for receiving execution tasks from clients and an output buffer for providing output data to the clients.

FIG. 9 is a diagram of an illustrative data processing system that is coupled by a network to clients in a client server-configuration and that includes reconfigurable processors, a host processor, and a storage device that stores configuration files for configuring the reconfigurable processors.

FIG. 10A is a diagram of an illustrative synchronous mode by which a data processing system may receive offloaded tasks from a client in a client-server configuration.

FIG. 10B is a diagram of an illustrative asynchronous mode by which a data processing system may receive offloaded tasks from a client in a client-server configuration.

FIG. 11 is a diagram of an illustrative data exchange between a client, a server, and two applications according to the technology disclosed.

FIG. 12 is a diagram of an illustrative data exchange between a client, a server control thread of an application, a server CPU thread of the application, and a server reconfigurable processor thread of the application.

FIG. 13 is a flowchart showing illustrative operations that a client and a server perform in a client-server configuration when the client offloads an execution task for executing on the server.

FIG. 14 is a flowchart showing illustrative operations that a data processing system that is configured as a server in a client-server configuration performs for executing applications that a client can offload as execution tasks for execution on the server.

DETAILED DESCRIPTION

The following discussion is presented to enable any person skilled in the art to make and use the technology disclosed and is provided in the context of a particular application and its requirements. Various modifications to the disclosed implementations will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other implementations and applications without departing from the spirit and scope of the technology disclosed. Thus, the technology disclosed is not intended to be limited to the implementations shown but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Traditional compilers translate human-readable computer source code into machine code that can be executed on a Von Neumann computer architecture. In this architecture, a processor serially executes instructions in one or more threads of software code. The architecture is static and the compiler does not determine how execution of the instructions is pipelined, or which processor or memory takes care of which thread. Thread execution is asynchronous, and safe exchange of data between parallel threads is not supported.

Traditional high-performance computing (HPC) applications often involve complex calculations and data processing that are executed at high speeds. Examples for HPC applications include serialized compute-hungry scientific simulations. HPC applications often run on an array of supercomputer nodes or clusters.

Some applications may include HPC tasks as well as machine learning (ML) computation tasks, and an illustrative hybrid workflow may intertwine the execution of HPC tasks and ML computation tasks.

Applications for machine learning (ML) and artificial intelligence (AI) may require massively parallel computations, where many parallel and interdependent threads (meta-pipelines) exchange data, and training these neural network models can be computationally extremely demanding. The computations involved in neural network training often include lengthy sequences that are highly repetitive, and that do not depend on the internal results from other instances of the sequence. Such computations often can be parallelized by running different instances of the sequence on different machines. Typically, the algorithms share partial results periodically among the instances, so periodic sync-ups occur as the algorithm proceeds.

Mechanisms for parallelizing neural network training can be divided roughly into two groups: model parallelism and data parallelism. In practice, parallelization mechanisms are sometimes mixed and matched, using a combination of model parallelism and data parallelism.

With model parallelism, the network model is divided up and parts of it are allocated to different data processing systems, which are sometimes also referred to as “nodes”, “worker nodes”, or “machines”. In some versions the model is divided longitudinally, such that upstream portions of the model are executed by one data processing system, which passes its results to another data processing system that executes downstream portions of the model. In the meantime, the upstream data processing system can begin processing the next batch of training data through the upstream portions of the model. In other versions of model parallelism, the model may include branches which are later merged downstream. In such versions the different branches could be processed on different data processing systems.

With data parallelism, different instances of the same network model are programmed into different data processing systems. The different instances typically each process different batches of the training data, and the partial results are combined.

Thus, applications for machine learning (ML) and artificial intelligence (AI) are ill-suited for execution on Von Neumann computers including supercomputer nodes or clusters. They require architectures that are adapted for parallel processing, such as coarse-grained reconfigurable architectures (CGRAs) or graphic processing units (GPUs).

Reconfigurable processors, and especially CGRAs, often include specialized hardware elements such as computing and memory units that operate in conjunction with one or more software elements such as a host processor and attached host memory, and are particularly efficient for implementing and executing highly-parallel applications such as machine learning applications. Therefore, it is desirable to provide a new data processing system that is particularly suited for executing highly-parallel applications. The new data processing system should be available for receiving and executing such applications in cooperation with other systems. The new data processing system should provide for a flexible use of reconfigurable data-flow resources and leverage artificial intelligence (AI) to improve the execution of compute intensive applications such as machine-learning (ML) and training of neural networks. The new data processing system should provide for an integration with other systems in a new heterogeneous system having heterogeneous node types. Such a heterogeneous system should enable the execution of different types of a calculation on the desirable and efficient compute resource, thereby allowing each application to execute on the right mix of node types for its computational needs.

FIG. 1 illustrates an example data processing system 100 including a host processor 180, a reconfigurable processor such as a coarse-grained reconfigurable (CGR) processor 110, and an attached CGR processor memory 190. As shown, CGR processor 110 has a coarse-grained reconfigurable architecture (CGRA) and includes an array of CGR units 120 such as a CGR array. CGR processor 110 may include an input-output (I/O) interface 138 and a memory interface 139. Array of CGR units 120 may be coupled with (I/O) interface 138 and memory interface 139 via databus 130 which may be part of a top-level network (TLN). Host processor 180 communicates with I/O interface 138 via system databus 185, which may be a local bus as described hereinafter, and memory interface 139 communicates with attached CGR processor memory 190 via memory bus 195.

Array of CGR units 120 may further include compute units and memory units that are interconnected with an array-level network (ALN) to provide the circuitry for execution of a computation graph or a data flow graph that may have been derived from a high-level program with user algorithms and functions. A high-level program is source code written in programming languages like Spatial, Python, C++, and C. The high-level program and referenced libraries can implement computing structures and algorithms of machine learning models like AlexNet, VGG Net, GoogleNet, ResNet, ResNeXt, RCNN, YOLO, SqueezeNet, SegNet, GAN, BERT, ELMo, USE, Transformer, and Transformer-XL.

If desired, the high-level program may include a set of procedures, such as learning or inferencing in an AI or ML system. More specifically, the high-level program may include applications, graphs, application graphs, user applications, computation graphs, control flow graphs, data flow graphs, models, deep learning applications, deep learning neural networks, programs, program images, jobs, tasks and/or any other procedures and functions that may perform serial and/or parallel processing.

The architecture, configurability, and data flow capabilities of CGR array 120 enables increased compute power that supports both parallel and pipelined computation. CGR processor 110, which includes CGR arrays 120, can be programmed to simultaneously execute multiple independent and interdependent data flow graphs. To enable simultaneous execution, the data flow graphs may be distilled from a high-level program and translated to a configuration file for the CGR processor 110. In some implementations, execution of the data flow graphs may involve using more than one CGR processor 110.

Host processor 180 may be, or include, a computer such as further described with reference to FIG. 2 . Host processor 180 runs runtime processes, as further referenced herein. Therefore, host processor 180 or portions of host processor 180 are sometimes also referred to as a runtime processor. In some implementations, host processor 180 may also be used to run computer programs, such as the compiler further described herein with reference to FIG. 6 . In some implementations, the compiler may run on a computer that is similar to the computer described with reference to FIG. 2 , but separate from host processor 180.

The compiler may perform the translation of high-level programs to executable bit files. While traditional compilers sequentially map operations to processor instructions, typically without regard to pipeline utilization and duration (a task usually handled by the hardware), an array of CGR units 120 requires mapping operations to processor instructions in both space (for parallelism) and time (for synchronization of interdependent computation graphs or data flow graphs). This requirement implies that a compiler for the CGR array 120 decides which operation of a computation graph or data flow graph is assigned to which of the CGR units in the CGR array 120, and how both data and, related to the support of data flow graphs, control information flows among CGR units, and to and from host processor 180 and attached CGR processor memory 190.

CGR processor 110 may accomplish computational tasks by executing a configuration file (e.g., a processor-executable format (PEF) file). For the purposes of this description, a configuration file corresponds to a data flow graph, or a translation of a data flow graph, and may further include initialization data. A compiler compiles the high-level program to provide the configuration file. In some implementations described herein, a CGR array 120 is configured by programming one or more configuration stores with all or parts of the configuration file. Therefore, the configuration file is sometimes also referred to as a programming file.

A single configuration store may be at the level of the CGR processor 110 or the CGR array 120, or a CGR unit may include an individual configuration store. The configuration file may include configuration data for the CGR array and CGR units in the CGR array, and link the computation graph to the CGR array. Execution of the configuration file by CGR processor 110 causes the CGR array (s) to implement the user algorithms and functions in the data flow graph.

CGR processor 110 can be implemented on a single integrated circuit (IC) die or on a multichip module (MCM). An IC can be packaged in a single chip module or a multichip module. An MCM is an electronic package that may comprise multiple IC dies and other devices, assembled into a single module as if it were a single device. The various dies of an MCM may be mounted on a substrate, and the bare dies of the substrate are electrically coupled to the surface or to each other using for some examples, wire bonding, tape bonding or flip-chip bonding.

FIG. 2 illustrates an example of a computer 200, including an input device 210, a processor 220, a storage device 230, and an output device 240. Although the example computer 200 is drawn with a single processor 220, other implementations may have multiple processors. Input device 210 may comprise a mouse, a keyboard, a sensor, an input port (e.g., a universal serial bus (USB) port), and/or any other input device known in the art. Output device 240 may comprise a monitor, printer, and/or any other output device known in the art. Illustratively, part or all of input device 210 and output device 240 may be combined in a network interface, such as a Peripheral Component Interconnect Express (PCIe) interface suitable for communicating with CGR processor 110 of FIG. 1 .

Input device 210 is coupled with processor 220, which is sometimes also referred to as host processor 220, to provide input data. If desired, memory 226 of processor 220 may store the input data. Processor 220 is coupled with output device 240. In some implementations, memory 226 may provide output data to output device 240.

Processor 220 further includes control logic 222 and arithmetic and logic unit (ALU) 224. Control logic 222 may be operable to control memory 226 and ALU 224. If desired, control logic 222 may be operable to receive program and configuration data from memory 226. Illustratively, control logic 222 may control exchange of data between memory 226 and storage device 230. Memory 226 may comprise memory with fast access, such as static random-access memory (SRAM). Storage device 230 may comprise memory with slow access, such as dynamic random-access memory (DRAM), flash memory, magnetic disks, optical disks, and/or any other memory type known in the art. At least a part of the memory in storage device 230 includes a non-transitory computer-readable medium (CRM 235), such as used for storing computer programs. The storage device 230 is sometimes also referred to as host memory.

FIG. 3 illustrates example details of a CGR architecture 300 including a top-level network (TLN 330) and two CGR arrays (CGR array 310 and CGR array 320). A CGR array comprises an array of CGR units (e.g., pattern memory units (PMUs), pattern compute units (PCUs), fused-control memory units (FCMUs)) coupled via an array-level network (ALN), e.g., a bus system. The ALN may be coupled with the TLN 330 through several Address Generation and Coalescing Units (AGCUs), and consequently with input/output (I/O) interface 338 (or any number of interfaces) and memory interface 339. Other implementations may use different bus or communication architectures.

Circuits on the TLN in this example include one or more external I/O interfaces, including I/O interface 338 and memory interface 339. The interfaces to external devices include circuits for routing data among circuits coupled with the TLN 330 and external devices, such as high-capacity memory, host processors, other CGR processors, FPGA devices, and so on, that may be coupled with the interfaces.

As shown in FIG. 3 , each CGR array 310, 320 has four AGCUs (e.g., MAGCU1, AGCU12, AGCU13, and AGCU14 in CGR array 310). The AGCUs interface the TLN to the ALNs and route data from the TLN to the ALN or vice versa.

One of the AGCUs in each CGR array in this example is configured to be a master AGCU (MAGCU), which includes an array configuration load/unload controller for the CGR array. The MAGCU1 includes a configuration load/unload controller for CGR array 310, and MAGCU2 includes a configuration load/unload controller for CGR array 320. Some implementations may include more than one array configuration load/unload controller. In other implementations, an array configuration load/unload controller may be implemented by logic distributed among more than one AGCU. In yet other implementations, a configuration load/unload controller can be designed for loading and unloading configuration of more than one CGR array. In further implementations, more than one configuration controller can be designed for configuration of a single CGR array. Also, the configuration load/unload controller can be implemented in other portions of the system, including as a stand-alone circuit on the TLN and the ALN or ALNs.

The TLN 330 may be constructed using top-level switches (e.g., switch 311, switch 312, switch 313, switch 314, switch 315, and switch 316). If desired, the top-level switches may be coupled with at least one other top-level switch. At least some top-level switches may be connected with other circuits on the TLN, including the AGCUs, and external I/O interface 338.

Illustratively, the TLN 330 includes links (e.g., L11, L12, L21, L22) coupling the top-level switches. Data may travel in packets between the top-level switches on the links, and from the switches to the circuits on the network coupled with the switches. For example, switch 311 and switch 312 are coupled by link L11, switch 314 and switch 315 are coupled by link L12, switch 311 and switch 314 are coupled by link L13, and switch 312 and switch 313 are coupled by link L21. The links can include one or more buses and supporting control lines, including for example a chunk-wide bus (vector bus). For example, the top-level network can include data, request and response channels operable in coordination for transfer of data in any manner known in the art.

FIG. 4 illustrates an example CGR array 400, including an array of CGR units in an ALN. CGR array 400 may include several types of CGR unit 401, such as FCMUs, PMUs, PCUs, memory units, and/or compute units. For examples of the functions of these types of CGR units, see Prabhakar et al., “Plasticine: A Reconfigurable Architecture for Parallel Patterns”, ISCA 2017, Jun. 24-28, 2017, Toronto, ON, Canada.

Illustratively, each of the CGR units may include a configuration store 402 comprising a set of registers or flip-flops storing configuration data that represents the setup and/or the sequence to run a program, and that can include the number of nested loops, the limits of each loop iterator, the instructions to be executed for each stage, the source of operands, and the network parameters for the input and output interfaces. In some implementations, each CGR unit 401 comprises an FCMU. In other implementations, the array comprises both PMUs and PCUs, or memory units and compute units, arranged in a checkerboard pattern. In yet other implementations, CGR units may be arranged in different patterns.

The ALN includes switch units 403 (S), and AGCUs (each including two address generators 405 (AG) and a shared coalescing unit 404 (CU)). Switch units 403 are connected among themselves via interconnects 421 and to a CGR unit 401 with interconnects 422. Switch units 403 may be coupled with address generators 405 via interconnects 420. In some implementations, communication channels can be configured as end-to-end connections.

A configuration file may include configuration data representing an initial configuration, or starting state, of each of the CGR units 401 that execute a high-level program with user algorithms and functions. Program load is the process of setting up the configuration stores 402 in the CGR array 400 based on the configuration data to allow the CGR units 401 to execute the high-level program. Program load may also require loading memory units and/or PMUs.

In some implementations, a runtime processor (e.g., the portions of host processor 180 of FIG. 1 that execute runtime processes, which is sometimes also referred to as “runtime logic”) may perform the program load.

The ALN includes one or more kinds of physical data buses, for example a chunk-level vector bus (e.g., 512 bits of data), a word-level scalar bus (e.g., 32 bits of data), and a control bus. For instance, interconnects 421 between two switches may include a vector bus interconnect with a bus width of 512 bits, and a scalar bus interconnect with a bus width of 32 bits. A control bus can comprise a configurable interconnect that carries multiple control bits on signal routes designated by configuration bits in the CGR array's configuration file. The control bus can comprise physical lines separate from the data buses in some implementations. In other implementations, the control bus can be implemented using the same physical lines with a separate protocol or in a time-sharing procedure.

Physical data buses may differ in the granularity of data being transferred. In one implementation, a vector bus can carry a chunk that includes 16 channels of 32-bit floating-point data or 32 channels of 16-bit floating-point data (i.e., 512 bits) of data as its payload. A scalar bus can have a 32-bit payload and carry scalar operands or control information. The control bus can carry control handshakes such as tokens and other signals. The vector and scalar buses can be packet-switched, including headers that indicate a destination of each packet and other information such as sequence numbers that can be used to reassemble a file when the packets are received out of order. Each packet header can contain a destination identifier that identifies the geographical coordinates of the destination switch unit (e.g., the row and column in the array), and an interface identifier that identifies the interface on the destination switch (e.g., North, South, East, West, etc.) used to reach the destination unit.

A CGR unit 401 may have four ports (as drawn) to interface with switch units 403, or any other number of ports suitable for an ALN. Each port may be suitable for receiving and transmitting data, or a port may be suitable for only receiving or only transmitting data.

A switch unit 403, as shown in the example of FIG. 4 , may have eight interfaces. The North, South, East and West interfaces of a switch unit may be used for links between switch units 403 using interconnects 421. The Northeast, Southeast, Northwest and Southwest interfaces of a switch unit 403 may each be used to make a link with an FCMU, PCU or PMU instance 401 using one of the interconnects 422. Two switch units 403 in each CGR array quadrant have links to an AGCU using interconnects 420. The coalescing unit 404 of the AGCU arbitrates between the AGs 405 and processes memory requests. Each of the eight interfaces of a switch unit 403 can include a vector interface, a scalar interface, and a control interface to communicate with the vector network, the scalar network, and the control network. In other implementations, a switch unit 403 may have any number of interfaces.

During execution of a graph or subgraph in a CGR array 400 after configuration, data can be sent via one or more switch units 403 and one or more links 421 between the switch units to the CGR units 401 using the vector bus and vector interface(s) of the one or more switch units 403 on the ALN. A CGR array may comprise at least a part of CGR array 400, and any number of other CGR arrays coupled with CGR array 400.

A data processing operation implemented by CGR array configuration may comprise multiple graphs or subgraphs specifying data processing operations that are distributed among and executed by corresponding CGR units (e.g., FCMUs, PMUs, PCUs, AGs, and CUs).

FIG. 5 illustrates an example 500 of a PMU 510 and a PCU 520, which may be combined in an FCMU 530. PMU 510 may be directly coupled to PCU 520, or optionally via one or more switches. PMU 510 includes a scratchpad memory 515, which may receive external data, memory addresses, and memory control information (e.g., write enable, read enable) via one or more buses included in the ALN. PCU 520 includes two or more processor stages, such as SIMD 521 through SIMD 526, and configuration store 528. The processor stages may include ALUs, or SIMDs, as drawn, or any other reconfigurable stages that can process data.

Each stage in PCU 520 may also hold one or more registers (not drawn) for short-term storage of parameters. Short-term storage, for example during one to several clock cycles or unit delays, allows for synchronization of data in the PCU pipeline.

FIG. 6 shows a compute environment 600 that provides on-demand network access to a pool of reconfigurable data flow resources 678 that can be rapidly provisioned and released with minimal management effort or service provider interaction. The pool of reconfigurable data flow resources 678 includes CGR processor memory (e.g., attached CGR processor memory 190 of FIG. 1 ), arrays of CGR units, and busses (e.g., memory bus 195 of FIG. 1 and/or TLN 330 of FIG. 3 ) that couple the arrays of CGR units and the CGR processor memory.

The busses or transfer resources enable the arrays of CGR units to receive and send data. Examples of the busses include peripheral component interface express (PCIe) channels, direct memory access (DMA) channels, double data-rate (DDR) channels, Ethernet channels, and InfiniBand channels. In some implementations, the busses include at least one of a DMA channel, a DDR channel, a PCIe channel, an Ethernet channel, or an InfiniBand channel.

The arrays of CGR units (e.g., arrays of compute units and memory units) are arranged in one or more reconfigurable processors (e.g., CGR processor 110 of FIG. 1 ) and may be coupled with each other in a programmable interconnect fabric (e.g., ALN 120 of FIG. 1 ). In some implementations, the arrays of CGR units are aggregated as a uniform pool of resources that are assigned to the execution of user applications.

The CGR processor memory of the pool of reconfigurable data flow resources 678 may be usable by the arrays of CGR units to store data. Examples of the CGR processor memory include main memory (e.g., off-chip/external dynamic random-access memory (DRAM)) and/or local secondary storage (e.g., local disks (e.g., hard disk drive (HDD), solid-state drive (SSD))). The memory units of the arrays of CGR units may include PMUs, latches, registers, and/or caches (e.g., SRAM).

The pool of reconfigurable data flow resources 678 is dynamically scalable to meet the performance objectives of applications 602 (or user applications 602). In some implementations, the applications 602 access the pool of reconfigurable data flow resources 678 over one or more networks (e.g., Internet).

The pool of reconfigurable data flow resources 678 may have different compute scales and hierarchies according to different implementations of the technology disclosed.

In one example, the pool of reconfigurable data flow resources 678 is a node (or a single machine) as further described herein with reference to FIG. 9 . Illustratively, the node may include arrays of CGR units that are arranged in a plurality of reconfigurable processors, supported by bus and CGR processor memory. The node also includes a host processor (e.g., CPU) that exchanges data with the plurality of reconfigurable processors, for example, over a PCIe interface. The host processor includes a runtime processor that manages resource allocation, memory mapping, and execution of the configuration files for applications requesting execution from the host processor.

In another example, the pool of reconfigurable data flow resources 678 is a rack (or cluster) of nodes, such that each node in the rack runs a respective plurality of reconfigurable processors, and includes a respective host processor configured with a respective runtime processor. The runtime processors are distributed across the nodes and communicate with each other so that they have unified access to the reconfigurable processors attached not just to their own node on which they run, but also to the reconfigurable processors attached to every other node in the data center.

The nodes in the rack are connected, for example, over Ethernet or InfiniBand (IB). In yet another example, the pool of reconfigurable data flow resources 678 is a pod that comprises a plurality of racks. In yet another example, the pool of reconfigurable data flow resources 678 is a superpod that comprises a plurality of pods. In yet another example, the pool of reconfigurable data flow resources 678 is a zone that comprises a plurality of superpods. In yet another example, the pool of reconfigurable data flow resources 678 is a data center that comprises a plurality of zones.

Users may execute applications 602 on the compute environment 600. Therefore, applications 602 are sometimes also referred to as user applications. The applications 602 are executed on the pool of reconfigurable data flow resources 678 in a distributed fashion by programming the individual compute and memory components to asynchronously receive, process, and send data and control information.

In the pool of reconfigurable data flow resources 678, computation can be executed as deep, nested data flow pipelines that exploit nested parallelism and data locality very efficiently. These data flow pipelines contain several stages of computation, where each stage reads data from one or more input buffers with an irregular memory access pattern, performs computations on the data while using one or more internal buffers or scratchpad memory to store and retrieve intermediate results, and produce outputs that are written to one or more output buffers. The structure of these pipelines depends on the control and data flow graph representing the application. Pipelines can be arbitrarily nested and looped within each other.

The applications 602 comprise high-level programs. A high-level program may include source code written in programming languages like C, C++, Java, JavaScript, Python, and/or Spatial, for example, using deep learning frameworks 614 such as PyTorch, TensorFlow, ONNX, Caffe, and/or Keras. The high-level program can implement computing structures and algorithms of machine learning models like AlexNet, VGG Net, GoogleNet, ResNet, ResNeXt, RCNN, YOLO, SqueezeNet, SegNet, GAN, BERT, ELMo, USE, Transformer, and/or Transformer-XL.

Software development kit (SDK) 642 generates computation graphs (e.g., data flow graphs, control graphs) 636 of the high-level programs of the applications 602. The SDK 642 transforms the input behavioral description of the high-level programs into an intermediate representation such as the computation graphs 636. This may include code optimization steps like false data dependency elimination, dead-code elimination, and constant folding. The computation graphs 636 encode the data and control dependencies of the high-level programs.

The computation graphs 636 comprise nodes and edges. The nodes can represent compute operations and memory allocations. The edges can represent data flow and flow control. In some implementations, each loop in the high-level programs can be represented as a “controller” in the computation graphs 636. The computation graphs 636 support branches, loops, function calls, and other variations of control dependencies. In some implementations, after the computation graphs 636 are generated, additional analyses or optimizations focused on loop transformations can be performed, such as loop unrolling, loop pipelining, loop fission/fusion, and loop tiling.

The SDK 642 also supports programming the reconfigurable data flow resources in the pool of reconfigurable data flow resources 678 at multiple levels, for example, from the high-level deep learning frameworks 614 to C++ and assembly language. In some implementations, the SDK 642 allows programmers to develop code that runs directly on the reconfigurable data flow resources. In other implementations, the SDK 642 provides libraries that contain predefined functions like linear algebra operations, element-wise tensor operations, non-linearities, and reductions that are used for creating, executing, and profiling the computation graphs 636 on the reconfigurable data flow resources. The SDK 642 communicates with the deep learning frameworks 614 via Application Programming Interfaces (APIs) 624.

A compiler 648 transforms the computation graphs 636 into a hardware-specific configuration, which is specified in an execution file 656 generated by the compiler 648. In one implementation, the compiler 648 partitions the computation graphs 636 into memory allocations and execution fragments, and these partitions are specified in the execution file 656. Execution fragments represent operations on data. An execution fragment can comprise portions of a program representing an amount of work. An execution fragment can comprise computations encompassed by a set of loops, a set of graph nodes, or some other unit of work that requires synchronization. An execution fragment can comprise a fixed or variable amount of work, as intended by the program. Different ones of the execution fragments can contain different amounts of computation. Execution fragments can represent parallel patterns or portions of parallel patterns and are executable asynchronously.

In some implementations, the partitioning of the computation graphs 636 into the execution fragments includes treating calculations within at least one innermost loop of a nested loop of the computation graphs 636 as a separate execution fragment. In other implementations, the partitioning of the computation graphs 636 into the execution fragments includes treating calculations of an outer loop around the innermost loop of the computation graphs 636 as a separate execution fragment. In the case of imperfectly nested loops, operations within a loop body up to the beginning of a nested loop within that loop body are grouped together as a separate execution fragment.

Memory allocations represent the creation of logical memory spaces in on-chip and/or off-chip memories for data used to implement the computation graphs 636, and these memory allocations are specified in the execution file 656. Memory allocations define the type and the number of hardware resources (functional units, storage, or connectivity components). Main memory (e.g., DRAM) is memory outside the reconfigurable processors for which the memory allocations can be made. Scratchpad memory (e.g., SRAM) is memory inside the reconfigurable processors for which the memory allocations can be made. Other memory types for which the memory allocations can be made for various access patterns and layouts include read-only lookup-tables (LUTs), fixed size queues (e.g., FIFOs), and register files.

The compiler 648 binds memory allocations to virtual memory units and binds execution fragments to virtual compute units, and these bindings are specified in the execution file 656. In some implementations, the compiler 648 partitions execution fragments into memory fragments and compute fragments, and these partitions are specified in the execution file 656.

The compiler 648 assigns the memory fragments to the virtual memory units and assigns the compute fragments to the virtual compute units, and these assignments are specified in the execution file 656. Each memory fragment is mapped operation-wise to the virtual memory unit corresponding to the memory being accessed. Each operation is lowered to its corresponding configuration intermediate representation for that virtual memory unit. Each compute fragment is mapped operation-wise to a newly allocated virtual compute unit. Each operation is lowered to its corresponding configuration intermediate representation for that virtual compute unit.

The compiler 648 allocates the virtual memory units to physical memory units of a reconfigurable processor (e.g., pattern memory units (PMUs) of the reconfigurable processor) and allocates the virtual compute units to physical compute units of the reconfigurable processor (e.g., pattern compute units (PCUs) of the reconfigurable processor), and these allocations are specified in the execution file 656. The compiler 648 places the physical memory units and the physical compute units onto positions in the arrays of CGR units of the pool of reconfigurable data flow resources and routes data and control networks between the placed positions, and these placements and routes are specified in the execution file 656.

The compiler 648 may translate the applications 602 developed with commonly used open-source packages such as Keras and/or PyTorch into reconfigurable processor specifications. The compiler 648 generates the configuration files with configuration data for the placed positions and the routed data and control networks. In one implementation, this includes assigning coordinates and communication resources of the physical memory and compute units by placing and routing units onto the arrays of the CGR units while maximizing bandwidth and minimizing latency.

A runtime processor 666 (e.g., host processor 180 of FIG. 1 executing runtime processes) receives the execution file 656 from the SDK 642 and uses the execution file 656 for resource allocation, memory mapping, and execution of the configuration files for the applications 602 on the pool of reconfigurable data flow resources 678. The runtime processor 666 may communicate with the SDK 642 over APIs 654 (e.g., Python APIs). If desired, the runtime processor 666 can directly communicate with the deep learning frameworks 614 over APIs 652 (e.g., C/C++ APIs).

In some implementations, a storage device may store a plurality of configuration files for a plurality of applications. If desired, the plurality of applications may include a collection of predetermined applications such as ML applications for which the SDK 642 and the compiler 648 have generated configuration files that are stored in the storage device. Illustratively, the storage device may store a first configuration file of the plurality of configuration files that is adapted for configuring the reconfigurable data flow resources 678 so that the reconfigurable data flow resources 678 are configured to execute a first application of the plurality of applications.

The runtime processor 666 may be operatively coupled to the pool of reconfigurable data flow resources 678 via a local bus 672. If desired, the local bus 672 may be a PCIe bus or any other local bus that enables the runtime processor 666 to exchange data with the pool of reconfigurable data flow resources 678.

The runtime processor 666 parses the execution file 656, which includes a plurality of configuration files. Configuration files in the plurality of configurations files include configurations of the virtual data flow resources that are used to execute the user applications 602. The runtime processor 666 allocates a subset of the arrays of CGR units in the pool of reconfigurable data flow resources 678 to the virtual data flow resources.

In some implementations, a storage device may store a plurality of configuration files, and the runtime processor 666 may receive an identifier of a predetermined application and retrieve a configuration file that is associated with the predetermined application from the storage device using the identifier of the predetermined application.

The runtime processor 666 then loads the configuration files for the applications 602 to the subset of the arrays of CGR units. In the scenario in which the execution file 656 includes two user applications 602 (e.g., a first and a second user application), the runtime processor 666 is configured to load a first configuration file for executing the first user application to a first subset of the arrays of CGR units in the pool of reconfigurable data flow resources 678, and to load a second configuration file for executing the second user application to a second subset of the arrays of CGR units in the pool of reconfigurable data flow resources 678. In some implementations, the CGR processor memory and the arrays of CGR units of the one or more reconfigurable processors in the pool of reconfigurable data flow resources 678 are aggregated as a uniform pool of resources that are assigned to the execution of the first and second user applications 602. The runtime processor 666 then starts execution of the user applications 602 on the subsets of the arrays of CGR units.

An application for the purposes of this description includes the configuration files for reconfigurable data flow resources in the pool of reconfigurable data flow resources 678 compiled to execute a mission function procedure or set of procedures such as inferencing or learning in an artificial intelligence or machine learning system. A virtual machine for the purposes of this description comprises a set of reconfigurable data flow resources (including arrays of CGR units in one or more reconfigurable processor, bus, and CGR processor memory) configured to support execution of an application in arrays of CGR units and associated bus and CGR processor memory in a manner that appears to the application as if there were a physical constraint on the resources available, such as would be experienced in a physical machine. The virtual machine can be established as a part of the application of the mission function that uses the virtual machine, or it can be established using a separate configuration mechanism. In implementations described herein, virtual machines are implemented using resources of the pool of reconfigurable data flow resources 678 that are also used in the application, and so the configuration files for the application include the configuration data for its corresponding virtual machine, and links the application to a particular set of CGR units in the arrays of CGR units and associated bus and CGR processor memory.

The runtime processor 666 may implement an application in a virtual machine. The virtual machine is allocated a particular set of CGR units, which can include some or all CGR units of a single reconfigurable processor or of multiple reconfigurable processors, along with associated bus and CGR processor memory (e.g., PCIe channels, DMA channels, DDR channels, DRAM memory).

FIG. 7A shows an illustrative system with heterogeneous node types. As shown, the illustrative system may include two supercomputer nodes 760, 765 and two reconfigurable processor nodes 710, 715. If desired, the illustrative system may include any compute units 760, 765 other than supercomputer nodes that offload execution tasks for execution on the reconfigurable processor nodes 710, 715. For example, the compute units 760, 765 may include mainframe computers, workstations, personal computers, quantum computers, etc.

The supercomputer nodes 760, 765 and the reconfigurable processor nodes 710, 715 may be located together in a same locality. As an example, the supercomputer nodes 760, 765 and the reconfigurable processor nodes 710, 715 may be located in the same system. As another example, the supercomputer nodes 760, 765 and the reconfigurable processor nodes 710, 715 may be housed in different systems that are located close to each other in a same physical location. If desired, the reconfigurable processor nodes 710, 715 may be located remotely from the supercomputer nodes 760, 765.

In some implementations, each one of the two reconfigurable processor nodes 710, 715 may be implemented by a pool of reconfigurable data flow resources (e.g., pool of reconfigurable data flow resources 678 of FIG. 6 ) that includes several reconfigurable processors together with associated reconfigurable processor memory. As an example, the reconfigurable processor nodes 710, 715 may each include 8 reconfigurable processors and 3 TB of memory. If desired, the reconfigurable processor nodes 710, 715 may be implemented using a different number of reconfigurable processors and/or a different amount of memory. For example, the reconfigurable processor nodes 710, 715 may each include 20 reconfigurable processors and 6 TB of memory. The reconfigurable processors may include any suitable type of coarse-grained reconfigurable processor and/or a mix of different types of coarse-grained reconfigurable processors. If desired, reconfigurable processor node 710 may include a different number of reconfigurable processors and/or a different amount of memory that reconfigurable processor node 715. Illustratively, the data processing system 100 of FIG. 1 or the data processing system 900 of FIG. 9 may implement reconfigurable processor nodes 710, 715. Therefore, a reconfigurable processor node is sometimes also referred to as “data processing system”.

Illustratively, the supercomputer nodes 760, 765 and the reconfigurable processor nodes 710, 715 may implement a client-server configuration in which the reconfigurable processor nodes 710, 715 act as servers 705 for the supercomputer node clients 755. Therefore, the reconfigurable processor nodes 710, 715 that act as servers 705 are sometimes also referred to as “server nodes”, and the compute units 760, 765 that act as clients 755 are sometimes also referred to as “client nodes”.

As shown in FIG. 7A, the client-server configuration includes two reconfigurable processor nodes 710, 715 that act as servers 705 and two supercomputer nodes 760, 765 that act as clients 755. However, the client-server configuration may include any number of reconfigurable processor nodes that act as servers and any number of supercomputer nodes that act as clients. As an example, the client-server configuration may include a single reconfigurable processor node that acts as server and a single supercomputer node that acts as client. As another example, the client-server configuration may include a single reconfigurable processor node that acts as server and N supercomputer nodes that act as clients, where N is an integer greater than one. As yet another example, the client-server configuration may include M reconfigurable processor nodes that act as servers, where M is an integer greater than one, and a single supercomputer node that acts as client. As yet another example, the client-server configuration may include M reconfigurable processor nodes that act as servers, where M is an integer greater than one, and N supercomputer nodes that act as client, where N is an integer greater than one. In some implementations, M is equal to N. In other implementations, M is not equal to N.

As shown in FIG. 7A, the clients 755 may offload execution tasks 730, 731, 733, 735 for execution on the servers 705, while the supercomputer nodes 760, 765 execute tasks 782, 786, respectively. In some implementations, tasks 782, 786 may pause while the offloaded execution tasks 730, 731, 733, 735 are executed by the reconfigurable processor nodes 710, 715.

Illustratively, the supercomputer nodes 760, 765 may include communication units 770, 790, respectively, that act as communication clients. Communication units 770, 790 may communicate with counterpart communication units 720, 728, 740, 748 that act as communication servers in the reconfigurable processor nodes 710, 715. For example, communication units 770, 790 and communication units 720, 728, 740, 748 may exchange data for the purpose of offloading and executing execution tasks from the clients 755 to the servers 705.

FIG. 7B is a diagram of illustrative communications in a client-server configuration in which two compute units 760, 765 (e.g., supercomputer nodes, mainframe computers, workstations, personal computers, quantum computers, etc.) that act as clients 755 offload execution tasks for execution on two reconfigurable processor nodes 710, 715 that act as servers 705. As shown in FIG. 7B, the client nodes 760, 765 and the server nodes 710, 715 are both initialized and set up during initialization operations 771, 791, 721, 741, respectively.

When a client node 760, 765 is ready to offload an execution task for execution on one of the server nodes 710, 715, the client node 760, 765 may connect with the server nodes 710, 715 during operations 772, 792, respectively. The server nodes 710, 715 may accept the connection during operations 722, 742, respectively, and confirm establishment of the connection back to the client nodes 760, 765.

In a next step, the client node 760, 765 may send the input parameters and an identifier for an application for execution to the server node 710, 715. As an example, consider the scenario in which client node 760 wants to offload execution tasks that include applications 732 and 734 for execution on server node 710, and client node 765 wants to offload execution tasks that include applications 736 and 738 for execution on server node 715. Illustratively, the applications 732, 734, 736, and/or 738 may include any computational tasks that are advantageously executed by reconfigurable processor nodes 710, 715. As an example, the computational task may include an ML task such as the stochastic gradient descent (SGD) or a deep learning task.

In this scenario, client node 760 may send 773 the input parameters and the identifier of application 732 to server node 710. The server node 710 may receive 723 the input parameters and the identifier of application 732, configure one or more reconfigurable processors with configuration data that is associated with application 732, execute application 732 on the one or more reconfigurable processors, and send 726 output data back to the client node 760, which may receive 776 the output data. Similarly, client node 760 may send 774 the input parameters and the identifier of application 734 to server node 710. The server node 710 may receive 724 the input parameters and the identifier of application 734, configure one or more reconfigurable processors with configuration data that is associated with application 734, execute application 734 on the one or more reconfigurable processors, and send 725 output data back to the client node 760, which may receive 775 the output data. Furthermore, client node 765 may send 793, 794 the input parameters and the identifiers of applications 736, 738 to server node 715. The server node 715 may receive 743, 744 the input parameters and the identifiers of applications 736, 738, configure for each one of applications 736, 738 one or more reconfigurable processors with configuration data that is associated with applications 736, 738, execute applications 736, 738 on the respective one or more reconfigurable processors, and send 745, 746 output data back to the client node 765, which may receive 795, 796 the output data.

FIG. 8 is a diagram of an illustrative client-server configuration in which an illustrative data processing system 805 is configured as a server in a client-server configuration and has buffers 810 for receiving input data from clients 860, 865 and for providing output data to clients 860, 865

In some implementations, clients 860, 865 may be located remotely from the data processing system 805. In other implementations, clients 860, 865 and the data processing system 805 may be located close to each other (e.g., in the same system or in different systems that are located close to each other in a same physical location).

Clients 860, 865 may be supercomputer nodes or any other computing nodes that perform computation tasks such as, for example, HPC tasks. If desired, clients 860, 865 may be any data processing nodes that offload execution tasks for execution on data processing system 805.

For example, clients 860, 865 may offload execution tasks that include one or more of applications App1 831, App2 832, App3 833, App4, 832, . . . , AppN 838 for execution onto data processing system 805. Illustratively, the applications 831 to 838 may include any computational task that is advantageously executed by data processing system 805. As an example, the computational task may include an ML task such as the stochastic gradient descent (SGD) or a deep learning task.

Consider the scenario in which applications 831 to 838 are executed continuously in a loop on the data processing system 805. Consider further that the clients 860, 865 are connected to the data processing system 805. In this scenario, the clients 860, 865 can send a request for any application of the applications 831 to 838 that are executing on the data processing system 805 (e.g., identified through an application identifier) together with input data.

As an example, client 860 wants to execute App1 831 and client 865 also wants to execute App1 831. The data processing system 805 may receive requests for executing App1 831 from the clients 860, 865, put the requests in a queue, and execute the application App1 in order in the data processing system 805.

As another example, client 860 wants to execute App1 831 and client 865 wants to execute App2 832. The data processing system 805 may receive requests for executing App1 831 from client 860 and for executing App2 832 from clients 865 and executes the applications App1 831 and App2 832 simultaneously, if no other clients are executing App1 831 and App2 832, in the data processing system 805.

Illustratively, there may be any combination between an arbitrary number of clients and an arbitrary number of applications that are being executed on the data processing system 805. As an example, a single client can execute one or more applications on the data processing system 805. If the single client executes more than one application, each one of the more than one application can be a different application. If desired, at least two of the more than one application can be a same application. As another example, multiple clients can execute the same application on the data processing system 805. If desired, at least one of the multiple clients may execute a different application on the data processing system 805 than the other ones of the multiple clients.

Once the data processing system 805 has finished executing the respective applications using the input data, the data processing system 805 sends the output data from the execution of the applications back to the clients 860, 865.

The data processing system 805 may include a reconfigurable processor. The reconfigurable processor may include arrays of coarse-grained reconfigurable CGR units. If desired, the reconfigurable processor may be CGR processor 110 of FIG. 1 that includes CGR arrays 120.

Data processing system 805 may include a predetermined number of reconfigurable processors. As an example, data processing system 805 may include eight reconfigurable processors. As another example, data processing system 805 may include 16, 32, 64, or more reconfigurable processors, whereby the number of reconfigurable processors is not limited to be a power of two. Instead, the data processing system 805 may include any number of reconfigurable processors.

Each reconfigurable processor in data processing system 805 may be partitionable into an arbitrary number of partitions that each can be independently configured and thus execute a different application of applications 831 to 838. If desired, each reconfigurable processor may be partitionable into a predetermined number of partitions. For example, the partitions may be arranged in a predetermined number of tiles that can be independently configured from each other.

As an example, consider the scenario in which the data processing system 805 includes eight reconfigurable processors that can each be partitioned into four partitions. In this scenario, the data processing system 805 may execute up to 32 applications in parallel. As another example, consider the scenario in which the data processing system 805 includes 16 reconfigurable processors, whereby the first eight of the 16 reconfigurable processors can each be partitioned into M partitions and the second eight of the 16 reconfigurable processors can each be partitioned into N partitions. In this scenario, the data processing system 805 may execute up to 8*(M+N) applications in parallel.

Illustratively, the data processing system 805 may include buffers 810 for facilitating data exchange between the clients 860, 865 and the data processing system 805. The buffers may operate in first-in, first-out (FIFO) mode. Buffers that operate in FIFO mode are sometimes also referred to as queues.

As shown in FIG. 8 , the data processing system 805 may include input buffers 821, 822, 823, 824, . . . , 828 for receiving execution tasks from clients 860, 865 and an output buffer 829 for providing output data to clients 860, 865.

In some implementations, the data processing system 805 may include one input buffer that operates in FIFO mode for every application 831 to 838 that can be executed on the data processing system 805. For example, the data processing system 805 may include N input buffers 821 to 828 if the data processing system 805 can execute N applications (e.g., applications 831 to 838), whereby each application App1 831, App2 832, App3 833, App4 834, . . . , and AppN 838 has an associated input buffer 821, 822, 823, 824, . . . , and 828 for receiving input data from a clients 860, 865. If desired, the number of input buffers may be configurable. For example, the number of input buffers may be selected to include a predetermined number of input buffers per input tensor per application.

Alternatively, the data processing system 805 may include one input buffer that operates in FIFO mode for every instance of an application that is being executed on the data processing system 805. As an example, the data processing system 805 may include five input buffers if the data processing system 805 is executing three instances of application App1 831 and two instances of application App2 832 at the same time, whereby each one of the three instances of application App1 831 has an associated buffer for receiving input data from a client 860, 865 and each one of the two instances of application App2 832 has an associated buffer for receiving input data from a client 860, 865. As another example, the data processing system 805 may include three input buffers if the data processing system 805 is executing one instance of each one of applications App1 831, App2 832, and AppN 838 at the same time, whereby each application App1 831, App2 832, and AppN 838 has an associated input buffer for receiving input data from a client 860, 865.

The data processing system 805 may include one output buffer 829 that receives the output data from the applications 831 to 838 that are being executed on the data processing system 805. If desired, the output buffer 829 operates in FIFO mode. The output data may be associated with identifying information to ensure that the output data can only be retrieved by an authorized client 860, 865. If desired, the data processing system 805 may include more than one output buffer. For example, the data processing system 805 may include as many output buffers as instances of applications are being executing on the data processing system 805. If desired, each instance of an application that is being executed on the data processing system 805 may be associated with a separate output buffer. Alternatively, the output data may be transferred directly from the device memory of the reconfigurable processor that executes the application (e.g., from CGR processor memory 190 that is associated with CGR processor 110 of FIG. 1 or from memory units in CGR array 120 of FIG. 1 ) to the client 860, 865. If desired, the number of output buffers may be configurable. For example, the number of output buffers may be selected to include a predetermined number of output buffers per output tensor per application.

Consider the scenario in which the data processing system 805 includes an input buffer per application that is executed on the data processing system 805. In this scenario, a client 860, 865 may send a request to the data processing system 805 for execution of an application. The request may include the identifier of the application (e.g., App1 831) and the address for writing the output data. In response, the data processing system 805 may decide to execute the application 831 on one of the reconfigurable processors. When the execution of the application 831 is finished, the output data may be written back from the device memory of the reconfigurable processor to the memory of the client 860, 865, whereby the output data may move directly from the reconfigurable processor memory in the data processing system 805 to the client 860 n 865, if desired.

If desired, the data processing system 805 may be ready to execute a predetermined number of applications (e.g., ML tasks) that are identified by an application identifier. If desired, each application may be associated with a graph or configuration file. The graph or configuration file may be used to configure the data processing system 805 such that the reconfigurable processor can execute the associated application.

Illustratively, the graph or configuration file may be stored in an archive for configuration files. The archive for configuration files may include one or more storage devices.

FIG. 9 is a diagram of an illustrative data processing system 900 that is configured as a server in a client-server configuration for executing a plurality of applications (e.g., App1, App2, . . . , AppN) that a client (e.g., client 960, 965, which is sometimes also referred to as client node 960, 965) in the client-server configuration can offload as execution tasks for execution on the server. In some implementations, a network 936 may couple the data processing system 900 with clients 960, 965 in the client server-configuration.

Examples of the network 936 include a Storage Area Network (SAN), a Local Area Network (LAN), and a Wide Area Network (WAN). The SAN can be implemented with a variety of data communications fabrics, devices, and protocols. For example, the fabrics for the SAN can include Fibre Channel, Ethernet, InfiniBand™, Serial Attached Small Computer System Interface (‘SAS’), or the like. Data communication protocols for use with the SAN can include Advanced Technology Attachment (‘ATA’), Fibre Channel Protocol, Small Computer System Interface (‘SCSI’), Internet Small Computer System Interface (‘iSCSI’), HyperSCSI, Non-Volatile Memory Express (‘NVMe’) over Fabrics, or the like.

The LAN can also be implemented with a variety of fabrics, devices, and protocols. For example, the fabrics for the LAN can include Ethernet (e.g., 802.3), wireless (e.g., 802.11), or the like. Data communication protocols for use in the LAN can include Transmission Control Protocol (‘TCP’), User Datagram Protocol (‘UDP’), Internet Protocol (IP), Hypertext Transfer Protocol (‘HTTP’), Wireless Access Protocol (‘WAP’), Handheld Device Transport Protocol (‘HDTP’), Session Initiation Protocol (‘SIP’), Real-time Transport Protocol (‘RTP’), or the like.

Illustratively, data may move directly between memory in the client nodes 960, 965 and memory in the data processing system 900, thereby providing for a low latency in executing tasks in the data processing system 900. As an example, the data may move directly between the memory in the client nodes 960, 965 and memory in the data processing system 900.

If desired, the connections between the client nodes 960, 965 and the data processing system 900 may be using a remote direct memory access (RDMA) connection. As an example, all the addresses of the client nodes 960, 965 and the data processing system 900 may be known at initialization. Illustratively, such addresses may be IP addresses or if it is an InfiniBand (IB) fabric, it may be IB addresses. Once all the addresses are known, the clients and servers may be connected via RDMA (e.g., using an RDMA application). The security of the communications between the clients and servers may be upheld by the secure nature of the RDMA connections. By way of example, the requests may be fully communicated by the client nodes for security reasons.

As shown in FIG. 9 , the data processing system 900 includes reconfigurable processors 942, a host processor 902, and a storage device 934. If desired, data processing system 900 may include a single reconfigurable processor. As shown in FIG. 9 , the data processing system 900 includes N reconfigurable processors RP1 to RP N, where N is an integer greater than one. In some implementations, the N reconfigurable processors 942 may be organized in a pool of reconfigurable data flow resources such as reconfigurable data flow resources 678 shown in FIG. 6 .

By way of example, the reconfigurable processors 942 are Coarse-Grained Reconfigurable Architecture (CGRA) devices. If desired, each reconfigurable processor 942 may include arrays of configurable units (e.g., compute units and memory units) in a programmable interconnect fabric. At least one of the reconfigurable processors 942 may be partitionable into a predetermined number of partitions. Each partition of the predetermined number of partitions may include at least one array of coarse-grained reconfigurable units. If desired, CGR processor 110 having arrays of CGR units 120 of FIG. 1 may implement the reconfigurable processors 942.

By way of example, the data processing system 900 may include reconfigurable processor memory 962. The reconfigurable processor memory 962 may include main memory such as dynamic random-access memory (DRAM), flash memory, magnetic disks (e.g., hard disk drive (HDD)), solid-state drives (SSD), optical disks, and/or any other memory type known in the art.

As shown in FIG. 9 , the reconfigurable processors 942 may interface with reconfigurable processor memory 962. For example, a memory interface such as memory interface 139 of FIG. 1 may couple the reconfigurable processors 942 with the reconfigurable processor memory 962. In some implementations, each reconfigurable processor of the reconfigurable processors 942 may interface with a respective separate reconfigurable processor memory 962. If desired, the reconfigurable processor memory 962 may be in the same package and/or on the same die as the associated reconfigurable processors 942. In other implementations, a single reconfigurable processor memory 962 may be associated with the reconfigurable processors 942.

In some implementations, the data processing system 900 includes a network interface controller (NIC) 932 that is sometimes also referred to as a “network interface card” 932. Illustratively, the network 936 may connect the NIC 932 with clients 960, 965. The network interface controller (NIC) 932 is operatively coupled to the reconfigurable processors 942 and to the host processor 902.

The host processor 902 is coupled to the storage device 934 and to the reconfigurable processors 942. In implementations described herein, the host processor 902 is coupled to a first local bus 925, the network interface controller (NIC) 932 is coupled to a second local bus 927, and the reconfigurable processors 942 are coupled to a third local bus 926. The local buses 925, 926, 927 may include a Peripheral Component Interconnect Express (PCIe) bus, a Cache Coherent Interconnect for Accelerators (CCIX) protocol bus, a Compute Express Link (CXL) connection, and/or an Open Coherent Accelerator Processor Interface (OpenCAPI). A bus switch 924 in the data processing system 900 a may couple the local buses 925, 926, 927, thereby coupling the host processor 902, the reconfigurable processors 942, and the network interface controller 932.

The storage device 934 stores a plurality of configuration files (e.g., conf(App1), conf(App2), conf(AppN)) for the plurality of applications. Illustratively, a first configuration file of the plurality of configuration files is adapted for configuring one or more of the reconfigurable processors 942 so that the one or more of the reconfigurable processors 942 is configured to execute a first application of the plurality of applications.

For example, the host processor 902 may be configured to receive a first execution task of the execution tasks with an identifier of the first application (e.g., App1) from the client 960, 965. For simplicity and brevity, the first application is described herein as being executed on a single reconfigurable processor of reconfigurable processors 942. However, without loss of generality, the first application may be executed on more than one reconfigurable processor of reconfigurable processors 942 or on a portion of a reconfigurable processor of reconfigurable processors 942.

In some implementations, the data processing system 900 may include a plurality of IP ports. If desired, the host processor 902 may be configured to receive the execution tasks for different applications of the plurality of applications on different IP ports of the plurality of IP ports.

In some scenarios, the data processing system 900 may include an input buffer that receives the first execution task. For example, the data processing system may include input buffers 821 to 828 of FIG. 8 and may receive the first execution task on input buffer 821. In these scenarios, the host processor 902 may be configured to execute a remote direct memory access operation to transfer input parameters for the first application (e.g., App1) from the client 960, 965 to the input buffer. The host processor 902 may further be configured to receive a status signal from the client 960, 965 indicating that the remote direct memory access operation has been completed.

In response to receiving the first execution task, the host processor 902 may retrieve the first configuration file (e.g., conf(App1)) from the storage device 934 using the identifier of the first application, configure the reconfigurable processor 942 with the first configuration file, and start execution of the first application on the reconfigurable processor 942. During and/or after the execution of the first application (e.g., App1) on the reconfigurable processor 942, the reconfigurable processor 942 may provide output data of the execution of the first application to the client 960, 965.

In some implementations, the data processing system 900 may include an output buffer (e.g., output buffer 829 of FIG. 8 ) for providing the output data to the client 960, 965. If desired, the reconfigurable processor 942 may be configured to write the output data to the output buffer, and send a status signal to the client 960, 965 indicating that the output data is ready to be retrieved.

If desired, the reconfigurable processor 942 may provide the output data in the output buffer with identifying information to ensure that the output data is provided to an authorized client of clients 960, 965 (i.e., a client that is authorized to access the output data).

When the data processing system 900 has finished the execution of the first application, and the output data has been transmitted to the client 960, 965, the client 960, 965 may tear down the current session with the server. In response, the host processor 902 may be configured to detect the tear down of the current session from the client 960, 965 and, in response to detecting the tear down of the current session, the host processor 902 may be configured to invalidate a cache of active session tokens.

Consider the scenario in which the input buffer receives a second execution task of the execution tasks with an identifier of a second application (e.g., App2) of the plurality of applications. In this scenario, the host processor 902 may be configured to pull the second execution task from the input buffer and execute another remote direct memory access operation to transfer additional input parameters for the second application from the client 960, 965 to the input buffer. In some implementations, the host processor may be configured to receive an additional status signal from the client 960, 965 indicating that the other remote direct memory access operation has been completed.

If desired, the host processor may be configured to retrieve the second configuration file (e.g., conf(App2)) from the storage device 934 using the identifier of the second application, configure the reconfigurable processor 942 with the second configuration file, and start execution of the second application on the reconfigurable processor 942 using the additional input parameters. During and/or after execution of the second application, the reconfigurable processor 942 may provide additional output data of the execution of the second application to the client 960, 965.

Illustratively, the clients 960, 965 may send tasks to the data processing system in a synchronous mode or in an asynchronous mode. FIG. 10A is a diagram of an illustrative synchronous mode by which a data processing system (e.g., data processing system 900 of FIG. 9 ) may receive offloaded tasks T0 and T1 from a client (e.g., client 960 of FIG. 9 ) in a client-server configuration. FIG. 10B is a diagram of an illustrative asynchronous mode by which a data processing system (e.g., data processing system 900 of FIG. 9 ) may receive offloaded tasks T0, T1, T2, and T3 from a client (e.g., client 960 of FIG. 9 ) in a client-server configuration.

The data processing system may perform a predetermined sequence of operations on the offloaded tasks T0 and T1 in FIG. 10A and T0 to T3 in FIG. 10B. For example, the data processing system may perform the operations “input data conversion”, “RDMA read operation”, “execution of application”, RDMA write operation”, and “output data conversion”. Illustratively, the data processing system waits until execution of an operation earlier in the sequence of operations has terminated before starting execution of an operation later in the sequence of operations. For example, the data processing system waits until the operation “input data conversion” has terminated on task TO before starting the operation “RDMA read operation” on task TO.

If desired, the data processing system may execute each operation of the predetermined sequence of operations independently from the other operations of the predetermined sequence of operations. For example, as shown in FIG. 10B, the data processing system may execute operation “execution of application” on task TO while executing operation “RDMA read operation” on task T1 and “input data conversion” on task T2.

As shown in FIG. 10A, in the synchronous mode, the client node may submit task T0 to the server node. The server node may start with the operation “input data conversion”, while the client node waits until the completion of the task on the server node, which may end with operation “output data conversion”. When the server node has completed task TO, the client node may submit the next task T1 to the server node. As shown in FIG. 10B, in the asynchronous mode, the client node may submit task T0 to the server node, which may start with operations “input data conversion”. The client node may wait until the completion of the operation “input data conversion” on T0, before submitting the next task T1 to the server node. In the asynchronous mode, the throughput of the server node may be significantly improved compared to the synchronous mode.

By way of example, the send/receive interface between compute units 760, 765 and reconfigurable processor nodes 710, 715 of FIG. 7B may be flexible enough to support both, an asynchronous and a synchronous operation mode. In the synchronous operation mode, after the client node 760 of FIG. 7 submits an (i−1)^(th) request to run a task (e.g., App 732) to the server node 710, the task 782 on client node 710 may be blocked until the (i−1)^(th) task is completed on the server node before the client node can submit an i^(th) request to run another task (e.g., App734) to the server node. In the asynchronous operation mode, the client node may submit an i^(th) requests to run a task (e.g., App 736) without the task 786 of client node 765 of FIG. 7 waiting on the completion of the previously submitted (i−1)^(th) request to run another task on the server node. The task on the client node can check request completion independent of the associated task execution on the server node, thereby allowing for desired flexibility and interoperability between tasks on the client nodes and tasks on the server node.

FIG. 11 is a diagram of an illustrative data exchange between a client 1150 (e.g., client 960 of FIG. 9 ), a server 1160 (e.g., data processing system 900 of FIG. 9 ), and two applications 1170, 1180 (e.g., App1 831 and App2 832 of FIG. 8 or App1 and App2 of FIG. 9 ) that are executing on the server 1160. As shown in FIG. 11 , the server 1160 sends requests 1112, 1114 for the device memory bus address to applications App1 1170 and App2 1180 and, in response, the server 1160 receives a respective device memory map 1118, 1116 from the applications App1 1170 and App2 1180.

The client 1150 may then issue a request 1122 to run application App1 1170 to the server 1160. For example, the client 1150 may send the identifier of the application together with the remote memory address to the server 1160. The server 1160 may add the new request to a queue (e.g., input queue 821 of FIG. 8 ) that is associated with application App1 1170.

When application App1 1170 becomes available, the server 1160 may pull the request for execution from the queue and retrieve the input data associated with the request for execution from the client 1150. For example, the server may perform an RDMA read operation 1124 using the remote memory address of the client 1150 on the remote node (e.g., client 960 of FIG. 9 ) and transfer the input data 1126 from the client 1150 to the reconfigurable processor memory (e.g., reconfigurable processor memory 952 of FIG. 9 ) that is associated with the execution of application App1 1170.

When all the input data has been transferred from the remote node to the reconfigurable processor memory, the client 1150 may issue a status signal 1128 that confirms the completion of the RDMA read operation. Upon reception of the status signal that confirms the completion of the RDMA read operation from the client 1150, the server 1160 may start execution 1132 of application App1 1170 on a reconfigurable processor (e.g., reconfigurable processor 942 of FIG. 9 ).

The reconfigurable processor may write output data 1134 such as the result from the execution of the application App1 1170 to the output buffer (e.g., output buffer 829 of FIG. 8 ) on the server 1160. The server 1160 may inform 1136 the client 1150 that output data is ready to be retrieved from the output queue. If desired, the server may write the output data to memory that is associated with the reconfigurable processor (e.g., reconfigurable processor memory). In response, the client 1150 may retrieve 1138 the output data from the output buffer (or from the reconfigurable processor memory).

FIG. 12 is a diagram of an illustrative data exchange between a client 1250, a server control thread of an application 1260, a server CPU thread of the application 1270, and a server reconfigurable processor thread of the application 1280. If desired, the application may be application App1 of FIG. 8 or FIG. 9 , and/or the data processing system 900 of FIG. 9 may be configured as the server, whereby the host processor 902 may execute the server control thread and the server CPU thread of the application 1270, and the reconfigurable processor 942 may execute the server reconfigurable processor thread of the application 1280.

As shown in FIG. 12 , the client 1250 may request to establish a session 1221 with the server for the execution of application App1 on a reconfigurable processor. If desired, the server may continuously listen to incoming requests on a well-defined IP port per application.

Upon reception of the request from a client, the server may spawn three threads: a control thread (e.g., Server Control Thread App1 1260), an administrative thread (e.g., Server CPU Thread App1 1270), and a reconfigurable processor thread (e.g., Server RDU Thread App1 1280). Illustratively, the administrative thread may retrieve a configuration file for application App1 (e.g., from memory) and configure the reconfigurable processor with the configuration file such that the reconfigurable processor can execute application App1. If desired, the configuration file may include a FIFO in a dedicated segment with compiler allocated virtual addresses (VA).

If desired, a host processor (e.g., host processor 902 of FIG. 9 ) may be configured to allocate physical addresses for a memory segment that is allocated to the execution of the application App1 on the reconfigurable processor. For example, the host processor may include a runtime processor that includes a kernel resource manager (KRM). The KRM may allocate physical addresses (PA) for a first-in first-out (FIFO) segment including a head pointer and a tail pointer that delimit the addresses that are allocated to the execution of application App1.

In some implementations, the reconfigurable processor may include a PCIe interface, and the runtime processor may program the PCIe base configuration and status registers (CSR) of the reconfigurable processor with the virtual addresses and an offset per FIFO. Illustratively, the runtime processor may program a segment lookaside buffer (SLB) which can hold the virtual to physical address mapping. For example, when an application (e.g., App1) starts execution on the reconfigurable processor, the application calls into a device driver in the KRM to memory map the PCIe physical base address register (BAR) region into its virtual address space and creates the virtual to physical mapping. Thereby, the physical address is calculated by adding the offset of the virtual address from the start of the virtual memory region to the start of the BAR physical address.

Illustratively, the reconfigurable processor may support a fixed sized memory mapped region. If desired, the fixed sized memory mapped region may be implemented in the PCIe BAR2 region, that exposes a “window” to the reconfigurable processor memory. This window is virtually contiguous. However, in the backend, the window may be implemented using a list of physically discontinuous regions (“window entries”) of a well-defined “page-size” using a “page-table” like interface

The server control thread 1260 may maintain a cache of active connections with session tokens 1241 and add a session token for the current session to the cache of active connections. The server control thread 1260 may confirm the establishment of the session 1222 by sending information regarding the input queue and the output queue to be used by the client to the client 1250, while the server reconfigurable processor thread 1280 is idle waiting for the arrival of input data.

After the establishment of the session, the client 1250 may start a remote set-get procedure 1242. During the remote set-get procedure, the client 1250 may send a remote set-get request 1223 together with a session identifier and input data to the server CPU thread 1270. If desired, the client 1250 may communicate the address of an output buffer where the client 1250 expects to receive the output data. The server CPU thread 1270 may put the remote set-get request together with the session identifier and the input data in a receive queue 1243.

The control is transferred 1224 from the server CPU thread 1270 to the server control thread 1260, which verifies 1244 whether the session that has been established between the client 1250 and the server is valid. Once the session has been confirmed to be valid, the server control thread 1260 informs 1225 the server CPU thread 1270 about the validity of the request to establish the current session.

In response to receiving the confirmation about the validly established session, the server CPU thread 1270 may start 1245 to initiate the RDMA read operation by sending an RDMA read request 1226 to the client 1250. The client 1250 then transfers input data from the client 1250 to the input buffer of the server 1227.

The client 1250 may transmit a status signal 1228 to the server CPU thread 1270 to indicate that the RDMA read operation has been completed. For example, the input buffer may be a FIFO, and the server CPU thread 1270 may initiate the RDMA read to the FIFO tail if the FIFO segment is empty. When the RDMA read operation from the client to the administrative thread is completed, the status signal may cause an update of the FIFO's tail pointer to instruct execution of application App1 on the reconfigurable processor.

Upon reception of this status signal, the server CPU thread 1270 may direct 1229 the server reconfigurable processor thread 1280 to execute application App1 on the reconfigurable processor 1246. Upon completion of the execution of application App1, the reconfigurable processor may initiate an RDMA write operation 1230, 1231 to the output buffer of the client, followed by a status signal 1232 indicating that the RDMA write operation has completed. For example, the output buffer may be a FIFO, and the administrative thread may wait for the FIFO tail pointer to update such that the reconfigurable processor has produced a new sample. When the FIFO tail pointer has finished updating, an RDMA write operation may be initiated from the FIFO head, followed by the status signal that may cause an update of the FIFO head pointer, which concludes the remote set-get procedure 1247.

Upon reception of all the output data from the server, the client 1250 may tear down the session 1233 to shut down the connection with the server. As a consequence of the termination of the session, the server may invalidate the cache of active session tokens 1248.

FIG. 13 is a flowchart showing illustrative operations that a client 1310 and a server 1320 perform in a client-server configuration when the client 1310 offloads an execution task for executing on the server 1320.

In some implementations, the client 1310 may include compute units such as compute units 760, 765 of FIG. 7A or 7B, which may include mainframe computers, workstations, personal computers, quantum computers, etc. Server 1320 may include a data processing system such as data processing system 100 of FIG. 1 , data processing system 805 of FIG. 8 , data processing system 900 of FIG. 9 , or a combination thereof. In some scenarios, the data processing system may include one or more reconfigurable processors. In these scenarios, the data processing system is sometimes also referred to as a reconfigurable processor node. If desired, InfiniBand (IB) channels may couple the client 1310 and the server 1320.

Illustratively, the server 1320 may start a runtime context and initiate a request queue. For example, the host processor 902 of FIG. 9 may start a runtime context by starting runtime processes and initiate a request queue such as one of input queues 821 to 828 of FIG. 8 . In a next operation, the server 1320 may find out which IB connection (i.e., which IB card) to use. The server 1320 may also determine a memory address for storing data on the reconfigurable processor memory.

When the client 1310 wants to offload the execution of a computational task to the server 1320, the client 1310 may contact 1311 the server 1320 to ask about the correct IB card to connect to. In response, the server 1320 may send 1321 the IP address of the correct IB card to the client 1310.

In another operation, the client 1320 may connect to the IB card and request 1333 for an RDMA connection from the server. The server 1320 may accept 1333 the RDMA connection and, as a result, spawn two separate threads, a server producer thread and a server consumer thread.

The client 1310 may send 1312 a remote inference request with input and output addresses on the remote host to the server producer thread. The server producer thread may acknowledge receipt of the request 1322, add the request to a request queue, and post receive requests for remote inference requests. In response to receiving the acknowledgement from the server producer thread, the client 1310 may post a receive request for remote inference request completion.

The server consumer thread may poll the request queue, and, upon detection of a request, read input data from the client. For example, the server consumer thread may perform an RDMA read operation 1313 to transfer data from the client's memory address to the reconfigurable processor memory address. The client may acknowledge the completion of the RDMA read operation 1323, and, in response to receiving the acknowledgement of completion, the server consumer thread may execute the application. If desired, the server may perform an RDMA read operation of the input data for the next request while the server 1320 is executing the application.

Upon completing the execution of the application, the server consumer thread may send output data to the client 1310. For example, the server consumer thread may perform an RDMA write operation 1314, thereby transferring data from the reconfigurable processor memory to the client's memory. The client 3110 may acknowledge reception 1324 of the output data. If desired, the server 1320 may perform an RDMA write operation of the output data from the current execution of the application while the server 1320 starts executing the next application. Thus, the server 1320 can increase the overall throughput by parallelizing RDMA read operations, RDMA write operations, and the execution of applications.

Upon reception of the acknowledgement from the client 1310, the server consumer thread may notify 1315 the client 1310 that the request has been completed. The client may acknowledge 1325 the completion of the request and search whether another remote inference request is ready to be sent to the server 1320, whereas the server consumer thread may return to polling the request queue.

FIG. 14 is a flowchart 1400 showing illustrative operations that a data processing system that is configured as a server in a client-server configuration performs for executing applications that a client can offload as execution tasks for execution on the server.

For example, the data processing system 900 of FIG. 9 may be configured as a server in a client-server configuration for executing a plurality of applications that client 960 and/or 965 in the client-server configuration can offload as execution tasks for execution on the server. As shown in FIG. 9 , such a data processing system may include a reconfigurable processor 942, a storage device 934 that stores a plurality of configuration files for a plurality of applications (e.g., conf(App1), conf(App2), . . . , conf(AppN)), whereby a first configuration file (e.g., conf(App1)) of the plurality of configuration files is adapted for configuring the reconfigurable processor 942 so that the reconfigurable processor 942 is configured to execute a first application (e.g., App1) of the plurality of applications, and a host processor 902 that is coupled to the storage device 934 and to the reconfigurable processor 942.

During operation 1410, the data processing system may receive a first execution task of the execution tasks with an identifier of the first application from the client. During operation 1420, the data processing system may retrieve, with the host processor, the first configuration file from the storage device using the identifier of the first application. For example, the host processor 902 of the data processing system 900 of FIG. 9 may retrieve the first configuration file conf(App1) from the storage device 934 using the identifier App1 of the first application.

During operation 1430, the data processing system may configure, with the host processor, the reconfigurable processor with the first configuration file. For example, the host processor 902 of the data processing system 900 of FIG. 9 may configure the reconfigurable processor 942 with the first configuration file conf(App1).

During operation 1440, the data processing system may start execution of the first application on the reconfigurable processor. For example, the data processing system 900 of FIG. 9 may start execution of application App1 on the reconfigurable processor 942.

During operation 1450, the data processing system may provide output data of the execution of the first application to the client. For example, the data processing system 900 of FIG. 9 may provide output data of the execution of the first application App1 to the client 960.

In some implementations, the data processing system may include an input buffer that receives the first execution task. In these implementations, the data processing system may execute a remote direct memory access operation to transfer input parameters for the first application from the client to the input buffer and receive a status signal from the client indicating that the remote direct memory access operation has been completed.

In some scenarios, the input buffer may receive a second execution task of the execution tasks with an identifier of a second application of the plurality of applications. In these scenarios, the data processing system may pull the second execution task from the input buffer, execute another remote direct memory access operation to transfer additional input parameters for the second application from the client to the input buffer, and receive an additional status signal from the client indicating that the other remote direct memory access operation has been completed.

If desired, the data processing system may retrieve, with the host processor, the second configuration file from the storage device using the identifier of the second application, configure, with the host processor, the reconfigurable processor with the second configuration file, start execution of the second application on the reconfigurable processor using the additional input parameters, and provide additional output data of the execution of the second application to the client.

Illustratively, the data processing system may detect a tear down of a current session from the client, and in response to detecting the tear down of the current session, invalidate a cache of active session tokens.

By way of example, the data processing system may determine physical addresses for a memory segment that is allocated to the execution of the first application on the reconfigurable processor.

Illustratively, the data processing system may program a segment lookaside buffer that holds a virtual to physical address mapping for the first application.

If desired, a non-transitory computer-readable storage medium includes instructions that, when executed by a processing unit (e.g., host processor 902 of FIG. 9 ), cause the processing unit to operate a data processing system (e.g., the data processing system 900 of FIG. 9 ) by performing operation 1410 to 1450 of FIG. 14 .

For example, a non-transitory computer-readable storage medium includes instructions that, when executed by a processing unit, cause the processing unit to operate a data processing system that is configured as a server in a client-server configuration for executing a plurality of applications that a client in the client-server configuration can offload as execution tasks for execution on the server. The data processing system includes a reconfigurable processor, a storage device, and a host processor that is coupled to the storage device and to the reconfigurable processor. The storage device stores a plurality of configuration files for a plurality of applications, whereby a first configuration file of the plurality of configuration files is adapted for configuring the reconfigurable processor so that the reconfigurable processor is configured to execute a first application of the plurality of applications.

The instructions may include receiving a first execution task of the execution tasks with an identifier of the first application from the client, retrieving the first configuration file from the storage device using the identifier of the first application, configuring the reconfigurable processor with the first configuration file, starting execution of the first application on the reconfigurable processor, and providing output data of the execution of the first application to the client.

While the present technology is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.

As will be appreciated by those of ordinary skill in the art, aspects of the presented technology may be embodied as a system, device, method, or computer program product apparatus. Accordingly, elements of the present disclosure may be implemented entirely in hardware, entirely in software (including firmware, resident software, micro-code, or the like) or in software and hardware that may all generally be referred to herein as a “apparatus,” “circuit,” “circuitry,” “module,” “computer,” “logic,” “FPGA,” “unit,” “system,” or other terms. Furthermore, aspects of the presented technology may take the form of a computer program product embodied in one or more computer-readable medium(s) having computer program code stored thereon. The phrases “computer program code” and “instructions” both explicitly include configuration information for a CGRA, an FPGA, or other programmable logic as well as traditional binary computer instructions, and the term “processor” explicitly includes logic in a CGRA, an FPGA, or other programmable logic configured by the configuration information in addition to a traditional processing core. Furthermore, “executed” instructions explicitly includes electronic circuitry of a CGRA, an FPGA, or other programmable logic performing the functions for which they are configured by configuration information loaded from a storage medium as well as serial or parallel execution of instructions by a traditional processing core.

Any combination of one or more computer-readable storage medium(s) may be utilized. A computer-readable storage medium may be embodied as, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or other like storage devices known to those of ordinary skill in the art, or any suitable combination of computer-readable storage mediums described herein. In the context of this document, a computer-readable storage medium may be any tangible medium that can contain, or store, a program and/or data for use by or in connection with an instruction execution system, apparatus, or device. Even if the data in the computer-readable storage medium requires action to maintain the storage of data, such as in a traditional semiconductor-based dynamic random-access memory, the data storage in a computer-readable storage medium can be considered to be non-transitory. A computer data transmission medium, such as a transmission line, a coaxial cable, a radio-frequency carrier, and the like, may also be able to store data, although any data storage in a data transmission medium can be said to be transitory storage. Nonetheless, a computer-readable storage medium, as the term is used herein, does not include a computer data transmission medium.

Computer program code for carrying out operations for aspects of the present technology may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, Python, C++, or the like, conventional procedural programming languages, such as the “C” programming language or similar programming languages, or low-level computer languages, such as assembly language or microcode. In addition, the computer program code may be written in VHDL, Verilog, or another hardware description language to generate configuration instructions for an FPGA, CGRA IC, or other programmable logic. The computer program code if converted into an executable form and loaded onto a computer, FPGA, CGRA IC, or other programmable apparatus, produces a computer implemented method. The instructions which execute on the computer, FPGA, CGRA IC, or other programmable apparatus may provide the mechanism for implementing some or all of the functions/acts specified in the flowchart and/or block diagram block or blocks. In accordance with various implementations, the computer program code may execute entirely on the user's device, partly on the user's device and partly on a remote device, or entirely on the remote device, such as a cloud-based server. In the latter scenario, the remote device may be connected to the user's device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). The computer program code stored in/on (i.e. embodied therewith) the non-transitory computer-readable medium produces an article of manufacture.

The computer program code, if executed by a processor, causes physical changes in the electronic devices of the processor which change the physical flow of electrons through the devices. This alters the connections between devices which changes the functionality of the circuit. For example, if two transistors in a processor are wired to perform a multiplexing operation under control of the computer program code, if a first computer instruction is executed, electrons from a first source flow through the first transistor to a destination, but if a different computer instruction is executed, electrons from the first source are blocked from reaching the destination, but electrons from a second source are allowed to flow through the second transistor to the destination. So, a processor programmed to perform a task is transformed from what the processor was before being programmed to perform that task, much like a physical plumbing system with different valves can be controlled to change the physical flow of a fluid.

Example 1 is a data processing system that is configured as a server in a client-server configuration for executing a plurality of applications that a client in the client-server configuration can offload as execution tasks for execution on the server, comprising: a reconfigurable processor; a storage device that stores a plurality of configuration files for the plurality of applications, wherein a first configuration file of the plurality of configuration files is adapted for configuring the reconfigurable processor so that the reconfigurable processor is configured to execute a first application of the plurality of applications; and a host processor that is coupled to the storage device and to the reconfigurable processor, and configured to: receive a first execution task of the execution tasks with an identifier of the first application from the client, retrieve the first configuration file from the storage device using the identifier of the first application, configure the reconfigurable processor with the first configuration file, and start execution of the first application on the reconfigurable processor, wherein the reconfigurable processor provides output data of the execution of the first application to the client.

In Example 2, the reconfigurable processor of Example 1 comprises arrays of coarse-grained reconfigurable (CGR) units.

In Example 3, the reconfigurable processor of Example 2 is partitionable into a predetermined number of partitions, wherein each partition of the predetermined number of partitions comprises at least one array of coarse-grained reconfigurable units.

In Example 4, the data processing system of Example 1 further comprises a plurality of IP ports, wherein the host processor is further configured to receive the execution tasks for different applications of the plurality of applications on different IP ports of the plurality of IP ports.

In Example 5, the data processing system of Example 1 further comprises an input buffer that receives the first execution task, and the host processor is further configured to: execute a remote direct memory access operation to transfer input parameters for the first application from the client to the input buffer, and receive a status signal from the client indicating that the remote direct memory access operation has been completed.

In Example 6, the input buffer of Example 5 receives a second execution task of the execution tasks with an identifier of a second application of the plurality of applications, and the host processor is further configured to: pull the second execution task from the input buffer; execute another remote direct memory access operation to transfer additional input parameters for the second application from the client to the input buffer; and receive an additional status signal from the client indicating that the other remote direct memory access operation has been completed.

In Example 7, the host processor of Example 6 is further configured to: retrieve the second configuration file from the storage device using the identifier of the second application; configure the reconfigurable processor with the second configuration file; and start execution of the second application on the reconfigurable processor using the additional input parameters, wherein the reconfigurable processor provides additional output data of the execution of the second application to the client.

In Example 8, the data processing system of Example 1 further comprises an output buffer for providing the output data to the client, and the reconfigurable processor is further configured to: write the output data to the output buffer, and send a status signal to the client indicating that the output data is ready to be retrieved.

In Example 9, the reconfigurable processor of Example 8 provides the output data in the output buffer with identifying information to ensure that the output data is provided to an authorized client.

In Example 10, the host processor of Example 1 is further configured to: detect a tear down of a current session from the client; and in response to detecting the tear down of the current session, invalidate a cache of active session tokens.

In Example 11, the host processor of Example 1 is further configured to: allocate physical addresses for a memory segment that is allocated to the execution of the first application on the reconfigurable processor.

In Example 12, the host processor of Example 1 is further configured to: program a segment lookaside buffer that holds a virtual to physical address mapping for the first application.

Example 13 is a method of operating a data processing system that is configured as a server in a client-server configuration for executing a plurality of applications that a client in the client-server configuration can offload as execution tasks for execution on the server, the data processing system comprising a reconfigurable processor, a storage device that stores a plurality of configuration files for a plurality of applications, wherein a first configuration file of the plurality of configuration files is adapted for configuring the reconfigurable processor so that the reconfigurable processor is configured to execute a first application of the plurality of applications, and a host processor that is coupled to the storage device and to the reconfigurable processor, the method comprising: receiving a first execution task of the execution tasks with an identifier of the first application from the client; retrieving, with the host processor, the first configuration file from the storage device using the identifier of the first application; configuring, with the host processor, the reconfigurable processor with the first configuration file; starting execution of the first application on the reconfigurable processor; and providing output data of the execution of the first application to the client.

In Example 14, the data processing system of Example 13 comprises an input buffer that receives the first execution task, and the method further comprises: executing a remote direct memory access operation to transfer input parameters for the first application from the client to the input buffer; and receiving a status signal from the client indicating that the remote direct memory access operation has been completed.

In Example 15, the input buffer of Example 14 receives a second execution task of the execution tasks with an identifier of a second application of the plurality of applications, and the method further comprises: pulling the second execution task from the input buffer; executing another remote direct memory access operation to transfer additional input parameters for the second application from the client to the input buffer; and receiving an additional status signal from the client indicating that the other remote direct memory access operation has been completed.

In Example 16, the method of Example 15 further comprises: retrieving, with the host processor, the second configuration file from the storage device using the identifier of the second application; configuring, with the host processor, the reconfigurable processor with the second configuration file; starting execution of the second application on the reconfigurable processor using the additional input parameters, and providing additional output data of the execution of the second application to the client.

In Example 17, the method of Example 13 further comprises: detecting a tear down of a current session from the client; and in response to detecting the tear down of the current session, invalidating a cache of active session tokens.

In Example 18, the method of Example 13 further comprises: determining physical addresses for a memory segment that is allocated to the execution of the first application on the reconfigurable processor.

In Example 19, the method of Example 13 further comprises: programming a segment lookaside buffer that holds a virtual to physical address mapping for the first application.

Example 20 is a non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a data processing system that is configured as a server in a client-server configuration for executing a plurality of applications that a client in the client-server configuration can offload as execution tasks for execution on the server, the data processing system comprising a reconfigurable processor, a storage device that stores a plurality of configuration files for a plurality of applications, wherein a first configuration file of the plurality of configuration files is adapted for configuring the reconfigurable processor so that the reconfigurable processor is configured to execute a first application of the plurality of applications, and a host processor that is coupled to the storage device and to the reconfigurable processor, the instructions comprising: receiving a first execution task of the execution tasks with an identifier of the first application from the client; retrieving the first configuration file from the storage device using the identifier of the first application; configuring the reconfigurable processor with the first configuration file; starting execution of the first application on the reconfigurable processor; and providing output data of the execution of the first application to the client. 

What is claimed is:
 1. A data processing system that is configured as a server in a client-server configuration for executing a plurality of applications that a client in the client-server configuration can offload as execution tasks for execution on the server, comprising: a reconfigurable processor; a storage device that stores a plurality of configuration files for the plurality of applications, wherein a first configuration file of the plurality of configuration files is adapted for configuring the reconfigurable processor so that the reconfigurable processor is configured to execute a first application of the plurality of applications; and a host processor that is coupled to the storage device and to the reconfigurable processor, and configured to: receive a first execution task of the execution tasks with an identifier of the first application from the client, retrieve the first configuration file from the storage device using the identifier of the first application, configure the reconfigurable processor with the first configuration file, and start execution of the first application on the reconfigurable processor, wherein the reconfigurable processor provides output data of the execution of the first application to the client.
 2. The data processing system of claim 1, wherein the reconfigurable processor comprises arrays of coarse-grained reconfigurable (CGR) units.
 3. The data processing system of claim 2, wherein the reconfigurable processor is partitionable into a predetermined number of partitions, wherein each partition of the predetermined number of partitions comprises at least one array of coarse-grained reconfigurable units.
 4. The data processing system of claim 1, further comprising: a plurality of IP ports, wherein the host processor is further configured to receive the execution tasks for different applications of the plurality of applications on different IP ports of the plurality of IP ports.
 5. The data processing system of claim 1, further comprising: an input buffer that receives the first execution task, and wherein the host processor is further configured to: execute a remote direct memory access operation to transfer input parameters for the first application from the client to the input buffer, and receive a status signal from the client indicating that the remote direct memory access operation has been completed.
 6. The data processing system of claim 5, wherein the input buffer receives a second execution task of the execution tasks with an identifier of a second application of the plurality of applications and wherein the host processor is further configured to: pull the second execution task from the input buffer; execute another remote direct memory access operation to transfer additional input parameters for the second application from the client to the input buffer; and receive an additional status signal from the client indicating that the other remote direct memory access operation has been completed.
 7. The data processing system of claim 6, wherein the host processor is further configured to: retrieve the second configuration file from the storage device using the identifier of the second application; configure the reconfigurable processor with the second configuration file; and start execution of the second application on the reconfigurable processor using the additional input parameters, wherein the reconfigurable processor provides additional output data of the execution of the second application to the client.
 8. The data processing system of claim 1, further comprising: an output buffer for providing the output data to the client, and wherein the reconfigurable processor is further configured to: write the output data to the output buffer, and send a status signal to the client indicating that the output data is ready to be retrieved.
 9. The data processing system of claim 8, wherein the reconfigurable processor provides the output data in the output buffer with identifying information to ensure that the output data is provided to an authorized client.
 10. The data processing system of claim 1, wherein the host processor is further configured to: detect a tear down of a current session from the client; and in response to detecting the tear down of the current session, invalidate a cache of active session tokens.
 11. The data processing system of claim 1, wherein the host processor is further configured to: allocate physical addresses for a memory segment that is allocated to the execution of the first application on the reconfigurable processor.
 12. The data processing system of claim 1, wherein the host processor is further configured to: program a segment lookaside buffer that holds a virtual to physical address mapping for the first application.
 13. A method of operating a data processing system that is configured as a server in a client-server configuration for executing a plurality of applications that a client in the client-server configuration can offload as execution tasks for execution on the server, the data processing system comprising a reconfigurable processor, a storage device that stores a plurality of configuration files for a plurality of applications, wherein a first configuration file of the plurality of configuration files is adapted for configuring the reconfigurable processor so that the reconfigurable processor is configured to execute a first application of the plurality of applications, and a host processor that is coupled to the storage device and to the reconfigurable processor, the method comprising: receiving a first execution task of the execution tasks with an identifier of the first application from the client; retrieving, with the host processor, the first configuration file from the storage device using the identifier of the first application; configuring, with the host processor, the reconfigurable processor with the first configuration file; starting execution of the first application on the reconfigurable processor; and providing output data of the execution of the first application to the client.
 14. The method of claim 13, wherein the data processing system comprises an input buffer that receives the first execution task, further comprising: executing a remote direct memory access operation to transfer input parameters for the first application from the client to the input buffer; and receiving a status signal from the client indicating that the remote direct memory access operation has been completed.
 15. The method of claim 14, wherein the input buffer receives a second execution task of the execution tasks with an identifier of a second application of the plurality of applications, further comprising: pulling the second execution task from the input buffer; executing another remote direct memory access operation to transfer additional input parameters for the second application from the client to the input buffer; and receiving an additional status signal from the client indicating that the other remote direct memory access operation has been completed.
 16. The method of claim 15, further comprising: retrieving, with the host processor, the second configuration file from the storage device using the identifier of the second application; configuring, with the host processor, the reconfigurable processor with the second configuration file; starting execution of the second application on the reconfigurable processor using the additional input parameters, and providing additional output data of the execution of the second application to the client.
 17. The method of claim 13, further comprising: detecting a tear down of a current session from the client; and in response to detecting the tear down of the current session, invalidating a cache of active session tokens.
 18. The method of claim 13, further comprising: determining physical addresses for a memory segment that is allocated to the execution of the first application on the reconfigurable processor.
 19. The method of claim 13, further comprising: programming a segment lookaside buffer that holds a virtual to physical address mapping for the first application.
 20. A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a data processing system that is configured as a server in a client-server configuration for executing a plurality of applications that a client in the client-server configuration can offload as execution tasks for execution on the server, the data processing system comprising a reconfigurable processor, a storage device that stores a plurality of configuration files for a plurality of applications, wherein a first configuration file of the plurality of configuration files is adapted for configuring the reconfigurable processor so that the reconfigurable processor is configured to execute a first application of the plurality of applications, and a host processor that is coupled to the storage device and to the reconfigurable processor, the instructions comprising: receiving a first execution task of the execution tasks with an identifier of the first application from the client; retrieving the first configuration file from the storage device using the identifier of the first application; configuring the reconfigurable processor with the first configuration file; starting execution of the first application on the reconfigurable processor; and providing output data of the execution of the first application to the client. 